参数资料
型号: ISL6144IVZA-T
厂商: Intersil
文件页数: 2/30页
文件大小: 0K
描述: IC CTRLR MOSFET HV ORING 16TSSOP
标准包装: 2,500
应用: 电信/数据通信系统
FET 型: N 沟道
输出数: 1
内部开关:
延迟时间 - 开启: 1ms
延迟时间 - 关闭: 250ns
电源电压: 9 V ~ 75 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 带卷 (TR)
ISL6144
Ordering Information
PART NUMBER
(Notes 2, 3)
ISL6144IVZA (Note 1)
ISL6144IRZA (Note 1)
PART
MARKING
ISL61 44IVZ
ISL6144 IRZ
TEMP. RANGE
(°C)
-40 to +105
-40 to +105
PACKAGE
(Pb-free)
16 Ld TSSOP
20 Ld 5x5 QFN
PKG.
DWG. #
M16.173
L20.5x5
ISL6441EVAL1Z
Evaluation Platform
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6144 . For more information on MSL please see techbrief TB363 .
Pinouts
ISL6144
(16 LD TSSOP)
TOP VIEW
ISL6144
(20 LD 5x5 QFN)
TOP VIEW
GATE
1
16
VOUT
VIN
HVREF
NC
2
3
4
15
14
13
COMP
VSET
NC
VIN
HVREF
1
2
20
19
18
17
16
15 VOUT
14 COMP
NC
3
13 VSET
NC
NC
5
6
12
11
NC
NC
NC
NC
4
5
12 NC
11 NC
NC
7
10
NC
6
7
8
9
10
GND
8
9
FAULT
Pin Descriptions
TSSOP
QFN
PIN #
1
2
3
8
9
PIN #
19
1
2
7
9
SYMBOL
GATE
VIN
HVREF
GND
FAULT
FUNCTION
External FET Gate Drive
Power Supply Connection
Chip High Voltage Reference
Chip Ground Reference
Fault Output
DESCRIPTION
Allows active control of external N-Channel FET gate to perform ORing function.
Chip bias input. Also provides a sensing node for external FET control.
Low side of floating high voltage reference for all of the HV chip circuitry.
Chip ground reference point.
Provides an open drain active low output as an indication that a fault has
occurred: GATE is OFF (GATE < V IN + 0.37V) or other types of faults
resulting in V IN - V OUT > 0.41V.
14
13
VSET
Low Side Connection for
Resistor connected to COMP provides adjustable “Vd - Vs” trip level along
Trip Level
with pin COMP.
15
16
14
15
COMP
VOUT
High Side Connection for HS
Comparator Trip Level
Chip Bias and Load
Resistor connected to V OUT provides sense point for the adjustable Vd - Vs
trip level along with pin VSET.
Provides the second sensing node for external FET control and chip output
Connection
bias.
4, 5, 6, 7,
10, 11,
12, 13
3, 4, 5, 6, 8,
10, 11, 12,
16, 17,
NC
No Connection
18, 20
2
FN9131.7
October 6, 2011
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