参数资料
型号: ISL6144IVZA
厂商: Intersil
文件页数: 24/30页
文件大小: 0K
描述: IC CTRLR MOSFET ORING HV 16TSSOP
标准包装: 96
应用: 电信/数据通信系统
FET 型: N 沟道
输出数: 1
内部开关:
延迟时间 - 开启: 1ms
延迟时间 - 关闭: 250ns
电源电压: 9 V ~ 75 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 管件
产品目录页面: 1243 (CN2011-ZH PDF)
ISL6144
For a 12V to 24V Input:
The duration of the reverse current pulse is in the order of a
TABLE 2. INPUT VOLTAGE = 12V TO 24V
I Load_Max MOSFET PART NUMBER
15A IRF1503S (Note 17)
SUM110N03-03P (Note 18)
STB100NF03L-03 (Note 19)
N
1
1
1
few hundred nanoseconds and is normally kept well below
the current rating of the ORing MOSFET.
Reducing the value of V TH(HS) results in lower reverse
current amplitude and reduces transients on the common
bus voltage.
40A
75A
IRF1503S
SUM110N03-03P
STB100NF03L-03
IRF1503S
SUM110N03-03P
2
2
2
3
3
Just a reminder, this is not an operating scenario, but it is
rather a fault scenario and should not occur frequently. As
explained above, different power supplies have different
noise spectrum and might need adjustment of the V TH(HS) .
R 1 = ----------------------------------------------------------------- R 2 (EQ. 17)
STB100NF03L-03 3
NOTES:
17. V DSS = 30V; I D = 190A; r DS(ON) = 3.3m Ω
18. V DSS = 30V; I D = 110A; r DS(ON) = 2.6m Ω
19. V DSS = 30V; I D = 100A; r DS(ON) = 3.2m Ω
20. All Above listed r DS(ON) values are at V GS = 10V
Another important consideration when choosing the ORing
MOSFET is the forward voltage drop across the drain-
source. If this drop approaches the 0.41V limit, (which is
used in the V OUT fault monitoring mechanism), this will
result in a permanent fault indication. Normally, this voltage
drop is chosen to be less than 100mV.
Setting the External HS Comparator
Threshold Voltage
Typically, DC/DC modules used in redundant power systems
have some form of active current sharing to realize the full
benefit of this scheme including lower operating
temperatures, lower system failure rate, as well as better
transient response when load step is shared. Current
sharing is realized using different techniques; all of these
techniques will lead to similar modules operating under
similar conditions in terms of switching frequency, duty cycle,
output voltage and current. When paralleled modules are
current sharing, their individual output ripple will be similar in
amplitude and frequency and the common bus will have the
same ripple as these individual modules and will not cause
any of the turn-off mechanisms to be activated as the same
ripple will be present on both sensing nodes (V IN and
V OUT ). This would allow setting the high speed comparator
threshold (V TH(HS) ) to a very low value. As a starting point, a
V TH(HS) of 55mV could be used, the final value of this TH
will be system dependent and has to be finalized in the
system prototype stage. If the gate experiences false turn-off
due to system noise, the V TH(HS) has to be increased.
The following procedure can be used for V TH(HS) selection:
Choose a value of V TH(HS) such that the net HS comparator
threshold voltage is positive to allow turn-off only when V IN
is lower than COMP. Take into account the worst-case of the
HS Comp offset (V OS(HS) = +25mV to -40mV). A good
starting value is 55mV. The sum of R 1 and R 2 is not to
exceed 50k Ω . It is suggested to choose R 2 = 47.5k Ω and
calculate R 1 according to Equation 17:
V TH ( HS )
V REF ( VSET ) – V TH ( HS )
R 1 = 499 Ω
R 1 resistor connected between VOUT and COMP pins
R 2 resistor connected between COMP and VSET pins
V REF(VSET) = 5.3V
1. Operate all parallel feeds in current sharing mode (either
by using current sharing techniques or by simply
adjusting the voltages very close to each other for natural
current sharing).
2. Vary the load current from 1A to its maximum value,
monitor the gate voltages, and make sure all gates are on
(note that at very light loads the current sharing scheme
might stop functioning and only one feed carries this light
current, at this point gate voltages will be just above the
gate threshold, and even maybe one gate will be on while
the others are not).
3. If at medium to maximum load currents all feeds have
their gates on, then the chosen V TH(HS) is suitable.
4. If only one feed has its gate on, the threshold value is too
low and the gate is turning off due to power supply noise
and needs to be increased. Also, the feeds may not be
sharing the load current due to discrepancy in output
voltages and current sharing failure.
5. Verify the current sharing scheme and output voltages. If
r DS ( ON )
The reverse current peak can be estimated as:
V TH ( HS ) + V SD ± V OS ( HS )
I REVERSEP = ---------------------------------------------------------------------- ; where
V SD is the MOSFET forward voltage drop
V OS(HS) is the voltage offset of HS Comparator
24
(EQ. 16)
the output voltages and currents of each feed are equal
but one or more of the gates is still off, increase V TH(HS)
by increasing R 1 in 250 Ω to 500 Ω increments (this
increases V TH(HS) by 25mV to 50mV) until all feeds have
their FETs turned on.
FN9131.7
October 6, 2011
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