参数资料
型号: ISL6208CBZ-T
厂商: Intersil
文件页数: 13/13页
文件大小: 0K
描述: IC MOSFET DRVR SYNC BUCK 8-SOIC
标准包装: 2,500
配置: 高端和低端,同步
输入类型: PWM
延迟时间: 20ns
电流 - 峰: 2A
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 33V
电源电压: 4.5 V ~ 5.5 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
ISL6208, ISL6208B
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/11
DETAIL "A "
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
AREA
4.00 (0.157)
5.80 (0.228)
0.50 (0.20)
0.25 (0.01)
x 45°
3.80 (0.150)
8 °
1
2
3
0.25 (0.010)
0.19 (0.008)
TOP VIEW
SIDE VIEW “B”
2.20 (0.087)
SEATING PLANE
1
8
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
2
7
0.60 (0.023)
1.27 (0.050)
-C-
3
4
6
5
1.27 (0.050)
0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
13
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN9115.6
January 31, 2012
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