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| 型号： | ISL6210CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 9/10页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRIVER DUAL SYNC 16QFN |
| 标准包装： | 6,000 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 26ns |
| 电流 - 峰： | 2A |
| 配置数： | 2 |
| 输出数： | 4 |
| 高端电压 - 最大（自引导启动）： | 36V |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN-EP（4x4） |
| 包装： | 带卷 (TR) |
ISL6210
Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and the power devices
(both upper and lower FETs) could cause serious ringing,
exceeding absolute maximum rating of the devices. The
negative ringing at the edges of the PHASE node could add
charges to the bootstrap capacitor through the internal
bootstrap diode, in some cases, it could cause over stress
across BOOT and PHASE pins. Therefore, user should do a
careful layout and select proper MOSFETs and drivers. The
D 2 PAK and DPAK package MOSFETs have high parasitic
lead inductance, which can exacerbate this issue. FET
selection plays an important role in reducing PHASE ring. If
higher inductance FETs must be used, a Schottky diode is
recommended across the lower MOSFET to clamp negative
PHASE ring.
A good layout would help reduce the ringing on the phase
and gate nodes significantly:
? Avoid uses via for decoupling components across BOOT
and PHASE pins and in between VCC and GND pins. The
decoupling loop should be short.
? All power traces (UGATE, PHASE, LGATE, GND, VCC)
should be short and wide, and avoid using via; otherwise,
use two vias for interconnection when possible.
? Keep SOURCE of upper FET and DRAIN of lower FET as
close as thermally possible.
? Keep connection in between SOURCE of lower FET and
power ground wide and short.
? Input capacitors should be placed as close to the DRAIN
of upper FET and SOURCE of lower FETs as thermally
possible.
NOTE: Refer to Intersil Tech Brief TB447 for more information.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
pad of the QFN part to the power ground with multiple vias is
recommended. This heat spreading allows the part to
achieve its full thermal potential.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN6392.1
December 9, 2008
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