参数资料
型号: ISL6218CRZ
厂商: Intersil
文件页数: 5/19页
文件大小: 0K
描述: IC CTRLR IMPVP-IV SGL-PHS 40-QFN
标准包装: 50
应用: 处理器
电流 - 电源: 1.4mA
电源电压: 4.75 V ~ 5.25 V
工作温度: -10°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN 裸露焊盘(6x6)
包装: 管件
ISL6218
Functional Pin Description 38 Ld TSSOP
VSEN
This pin is used for remote sensing of the microprocessor
VDD
DACOUT
DSV
FSET
NC
EN
DRSEN
DSEN
VID0
1
2
3
4
5
6
7
8
9
38 VBAT
37 ISEN
36 PHASE
35 UG
34 BOOT
33 VSSP
32 LG
31 VDDP
30 NC
CORE voltage.
COMP
This pin provides connection to the error amplifier output.
FB
This pin is connected to the inverting input of the error
amplifier.
EA+
VID1
VID2
VID3
VID4
VID5
PGOOD
EA+
COMP
FB
SOFT
10
11
12
13
14
15
16
17
18
19
ISL6218
29 NC
28 NC
27 NC
26 NC
25 NC
24 VSEN
23 DRSV
22 STV
21 OCSET
20 VSS
This pin is connected to the non-inverting input of the error
amplifier and is used for setting the “Droop” voltage.
STV
The voltage on this pin sets the initial start-up or “Boot”
voltage.
SOFT
This pin programs the slew rate of VID changes, Deep Sleep
and Deeper Sleep transitions, and soft-start after initializing.
This pin is connected to ground via a capacitor, and to EA+
through an external “Droop” resistor.
VDD
This pin is used to connect +5V to the IC to supply all power
necessary to operate the chip. The IC starts to operate when
the voltage on this pin exceeds the rising POR threshold and
shuts down when the voltage on this pin drops below the
falling POR threshold.
VDDP
This pin provides a low ESR bypass connection to the
internal gate drivers for the +5V source.
PGOOD
This pin is used as an input and an output and is tied to the
Vccp and Vcc_mch PGOOD signals. During start-up, this pin
is recognized as an input, and prevents further slewing of the
output voltage from the “Boot” level until PGOOD from Vccp
and Vcc_mch is enabled High. After start-up, this pin has an
open drain output used to indicate the status of the CORE
output voltage. This pin is pulled low when the system output
is outside of the regulation limits. PGOOD includes a timer
for power-on delay.
EN
This pin is connected to the system signal VR_ON and
provides the enable/disable function for the PWM controller.
OCSET
A resistor from this pin to ground sets the overcurrent
protection threshold. The current from this pin should be
between 10μA and 25μA (70k Ω to 175k Ω equivalent
pull-down resistance).
5
DSEN
This pin connects to system logic “STP_CPU” and enables
Deep Sleep mode of operation. Deep Sleep is enabled when
a logic LOW signal is detected on this pin.
DRSEN
This pin connects to system logic “DPRSLPVR” and enables
Deeper Sleep mode of operation when a logic HIGH is
detected on this pin.
VBAT
Voltage on this pin provides feed-forward battery information
that adjusts the oscillator ramp amplitude.
FSET
A resistor from this pin to ground programs the switching
frequency.
ISEN
This pin is used as current sense input from the converter
channel phase node.
DACOUT
This pin provides access to the output of the Digital-to-
Analog Converter.
DSV
The voltage on this pin provides the setpoint for output
voltage during Deep Sleep Mode of operation.
DRSV
The voltage on this pin provides the setpoint for output
voltage during Deeper Sleep Mode of operation.
FN9101.6
August 6, 2007
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