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参数资料
| 型号： | ISL6223CAZA-T |
| 厂商： | Intersil |
| 文件页数： | 7/15页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 20-SSOP |
| 标准包装： | 2,500 |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 频率 - 最大： | 305kHz |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
pulse width of the Comparator to compensate for the
detected “above average” current in that channel.
Droop Compensation
In addition to control of each power channel’s output current,
the average channel current is also used to provide CORE
voltage “droop” compensation. Average full channel current
is defined as 50 μ A. By selecting an input resistor, R IN , the
amount of voltage droop required at full load current can be
programmed. The average current driven into the FB pin
results in a voltage increase across resistor R IN that is in the
direction to make the Error Amplifier “see” a higher voltage
at the inverting input, resulting in the Error Amplifier
adjusting the output voltage lower. The voltage developed
across R IN is equal to the “droop” voltage. See the “Current
Sensing and Balancing” section for more details.
Applications and Convertor Start-Up
Each PWM power channel’s current is regulated. This
enables the PWM channels to accurately share the load
current for enhanced reliability. The HIP6601, HIP6602 or
HIP6603 MOSFET driver interfaces with the ISL6223. For
more information, see the HIP6601, HIP6602 or HIP6603
data sheets.
The ISL6223 controls the two PWM power channels 180°
out of phase. Figure 2 shows the out of phase relationship
between the two PWM channels.
PWM 1
PWM 2
FIGURE 2. TWO PHASE PWM OUTPUT AT 500kHz
Power supply ripple frequency is determined by the channel
frequency, F SW , multiplied by the number of active channels.
For example, if the channel frequency is set to 250kHz, the
ripple frequency is 500kHz with two channels.
The IC monitors and precisely regulates the CORE voltage
of a microprocessor. After initial start-up, the controller also
provides protection for the load and the power supply. The
following section discusses these features.
Initialization
The ISL6223 operates from a 5V power supply. Many
functions are initiated by the rising supply voltage to the V CC
pin of the ISL6223. Oscillator, Sawtooth Generator, Soft-
Start and other functions are initialized during this interval.
These circuits are controlled by POR, Power-On Reset.
During this interval, the PWM outputs are driven to a three
7
state condition that makes these outputs essentially open.
This state results in no gate drive to the output MOSFETs.
Once the V CC voltage reaches 4.375V (+125mV), a voltage
level to insure proper internal function, the PWM outputs are
enabled and the Soft-Start sequence is initiated. If for any
reason, the V CC voltage drops below 3.875V (+125mV). The
POR circuit shuts the converter down and again three states
the PWM outputs.
Soft-Start
After the POR function is completed with V CC reaching
4.375V, the Soft-Start sequence is initiated. Soft-Start, by its
slow rise in CORE voltage from zero, avoids an overcurrent
condition by slowly charging the discharged output
capacitors. This voltage rise is initiated by an internal DAC
that slowly raises the reference voltage to the error amplifier
input. The voltage rise is controlled by the oscillator
frequency and the DAC within the ISL6223, therefore, the
output voltage is effectively regulated as it rises to the final
programmed CORE voltage value.
For the first 64 PWM switching cycles, the DAC output
remains inhibited and the PWM outputs remain three stated.
From the 65th cycle and for another, approximately 300
cycles the PWM output remains low, clamping the lower
output MOSFETs to ground, see Figure 3. The time
variability is due to the Error Amplifier, Sawtooth Generator
and Comparators moving into their active regions. After this
short interval, the PWM outputs are enabled and increment
the PWM pulse width from zero duty cycle to operational
pulse width, thus allowing the output voltage to slowly reach
the CORE voltage. The CORE voltage will reach its
programmed value before the 4096 cycles, but the PGOOD
output will not be initiated until the 4096th switching cycle.
The Soft-Start time or delay time, DT = 4096/F SW . For an
oscillator frequency, F SW , of 200kHz, the first 64 cycles or
320 μ s, the PWM outputs are held in a three state level as
explained above. After this period and a short interval
described above, the PWM outputs are initiated and the
voltage rises in 20.16ms, for a total delay time DT of
20.48ms.
Figure 3 shows the start-up sequence as initiated by an
enable (EN) switch , applied to the ISL6223. The start-up is
enabled at the falling edge of the EN switch output.
Figure 4 shows the waveforms when the regulator is
operating at 200kHz. Note that the Soft-Start duration is a
function of the Channel Frequency as explained previously.
Also note the pulses on the COMP terminal. These pulses
are the current correction signal feeding into the comparator
input (see the “Block Diagram” on page 2).
Figure 5 shows the regulator operating from a 12V battery
supply. In this system, the battery voltage is available before
any other voltages, including the 5V bias voltage V CC for the
controller IC. In this figure, note the slight rise in PGOOD as
FN9013.3
July 9, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6223EVAL1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Mobile Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller |
| ISL6223EVAL2 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Mobile Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller |
| ISL6224 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Single Output Mobile-Friendly PWM Controller |
| ISL6224_06 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Single Output Mobile-Friendly PWM Controller |
| ISL6224CA | 功能描述:电流型 PWM 控制器 Mobile-Friendly RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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