参数资料
| 型号： | ISL6225CAZA-T |
| 厂商： | Intersil |
| 文件页数： | 10/19页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR DDR DRAM, SDRAM 28QSOP |
| 标准包装： | 2,500 |
| 应用： | 控制器，DDR DRAM，SDRAM |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 2 |
| 输出电压： | 0.9 V ~ 5.5 V |
| 工作温度： | -10°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 28-SSOP/QSOP |
| 包装： | 带卷 (TR) |
ISL6225
R CS = --------------------------------------------- ) - – 100 ?
F PO = ----------------------------------
F Z = ------------------------------- = 6kHz
The hysteretic comparator initiates the PWM signal when the
output voltage gets below the lower threshold and
terminates the PWM signal when the output voltage rises
above the upper threshold. A spread or hysteresis between
these two thresholds determines the switching frequency
and the peak value of the inductor current. The transition to
constant frequency CCM mode happens when the inductor
current increases above the critical value:
? V hys
2 ? ESR
I CCM ≈ ----------------------
Where, ? V hys = 15mV, is a hysteretic comparator window,
ESR is the equivalent series resistance of the output
capacitor. Because of different control mechanisms, the
value of the load current where transition into CCM
operation takes place is usually higher compared to the load
level at which transition into hysteretic mode had occurred.
V OUT pin and Forced Continuous
Conduction Mode (FCCM)
The controller has the flexibility to operate a converter in
fixed-frequency constant conduction mode (CCM), or in
hysteretic mode. Connecting the V OUT pin to GND will inhibit
hysteretic mode; this is called forced constant conduction
mode (FCCM). Connecting the V OUT pin to the converter
output will allow transition between CCM mode and
an internal current control loop. The resistor connected to
the ISEN pin sets the gain in the current feedback loop. The
following expression estimates the required value of the
current sense resistor depending on the maximum load
current and the value of the MOSFET’s r DS(ON) .
I MAX ? r DS ( ON
75 μ A
Due to implemented current feedback, the modulator has a
single pole response with -1 slope at a frequency
determined by the load,
1
2 π ? RO ? CO
where: Ro is load resistance and Co is load capacitance. For
this type of modulator, a Type 2 compensation circuit is
usually sufficient.
Figure 7 shows a Type 2 amplifier and its response along
with the responses of the current mode modulator and the
converter. The Type 2 amplifier, in addition to the pole at
origin, has a zero-pole pair that causes a flat gain region at
frequencies between the zero and the pole:
1
2 π ? R2 ? C1
hysteretic mode.
;
F P = ------------------------------- = 600kHz
When the V OUT pin is connected to the converter output, a
circuit is activated that smooths the transition from hysteretic
mode to CCM mode. While in hysteretic mode, this circuit
prepositions the PWM error amplifier output to a level close
to that needed to provide the appropriate PWM duty cycle
required for regulation. This is a much more desirable state
for the PWM error amplifier at mode transition, as opposed
to being in saturation which requires a period of time to slew
to the required level.
1
2 π ? R1 ? C2
This region is also associated with phase ‘bump’ or
reduced phase shift. The amount of phase shift reduction
depends on how wide the region of flat gain is and has a
maximum value of 90 o . To further simplify the converter
compensation, the modulator gain is kept independent of
the input voltage variation by providing feed-forward of V IN
to the oscillator ramp.
Such dual function of the V OUT pin enhances applicability of
the controller and allows for lower pin count.
Feedback Loop Compensation
CONVERTER
R1
R2
C2
C1
To reduce the number of external components and remove
the burden of determining compensation components from a
system designer, both PWM controllers have internally
compensated error amplifiers. To make internal
compensation possible several design measures where
taken.
First, the ramp signal applied to the PWM comparator is
proportional to the input voltage provided via the VIN pin.
This keeps the modulator gain constant when the input
voltage varies. Second, the load current proportional signal
is derived from the voltage drop across the lower MOSFET
EA
G M = 18dB
MODULATOR
F PO
F Z
TYPE 2 EA
G EA = 14dB
F C
F P
during the PWM time interval and is added to the amplified
error signal on the comparator input. This effectively creates
10
FIGURE 7. FEEDBACK LOOP COMPENSATION
FN9049.7
December 28, 2004
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| ISL6225CAZ-T | 功能描述:IC CTRLR DDR DRAM, SDRAM 28QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6226 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced PWM and Linear Power Controller for Portable Applications |
| ISL6226CA | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intersil Corporation 功能描述: |
| ISL6226EVAL1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Advanced PWM and Linear Power Controller for Portable Applications |
| ISL6227 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual Mobile-Friendly PWM Controller with DDR Option |
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