参数资料
型号: ISL6225CAZA-T
厂商: Intersil
文件页数: 7/19页
文件大小: 0K
描述: IC CTRLR DDR DRAM, SDRAM 28QSOP
标准包装: 2,500
应用: 控制器,DDR DRAM,SDRAM
输入电压: 5 V ~ 24 V
输出数: 2
输出电压: 0.9 V ~ 5.5 V
工作温度: -10°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.154",3.90mm 宽)
供应商设备封装: 28-SSOP/QSOP
包装: 带卷 (TR)
Block Diagram
BOOT1
SOFT1
PG1
EN1 VOUT1
VCC GND
VOUT2
EN2
REF/PG2
SOFT2
BOOT2
UGATE1
UGATE2
PHASE1
PGND1
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
DDR=0
DDR=1
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
PHASE2
PGND2
LGATE1
PWM/HYS TRANSITION
PWM/HYS TRANSITION
LGATE2
VCC
POR
VCC
MODE CHANGE COMP 1
+
ENABLE
+
MODE CHANGE COMP 2
-
SAME STATE FOR
BIAS SUPPLIES
SAME STATE FOR
-
8 CLOCK CYCLES
8 CLOCK CYCLES
HYSTERETIC COMPARATOR 1
-
REQUIRED TO CHANGE
PWM OR HYS MODE
REFERENCE
REQUIRED TO CHANGE
PWM OR HYS MODE
- HYSTERETIC COMPARATOR 2
FAULT LATCH
+
? V HYS =15mV
? V HYS =15mV
+
SOFT-START
1M ?
15.2pF
OV UV
PGOOD
DDR MODE
CONTROL
OV UV
PGOOD
15.2pF
1M ?
500k ?
VOLTS/SEC
CLAMP
VOLTS/SEC
CLAMP
500k ?
VSEN1
300k ?
-
+
1.3pF
Σ
-
PWM1
OC1 DDR OC2
PWM2
-
Σ
1.3pF
-
+
300k ?
VSEN2
+
0.9V REFERENCE
ERROR AMP 1
+
+
ERROR AMP 2
DDR=0
DDR=1
DUTY CYCLE RAMP GENERATOR
PWM CHANNEL PHASE CONTROL
0.9V REFERENCE
+
DDR EN1 EN2
VIN
CH1CH2 φ
ISEN1
100 ?
0
1
1
0 ? 24.0V
180o
100 ?
ISEN2
CURRENT
SAMPLE
-
+
CURRENT
SAMPLE
1
1
1
4.2 < VIN < 24.0V
VIN to GND
0o
90o
CURRENT
SAMPLE
-
+
CURRENT
SAMPLE
OCSET1
DDR=0
OCSET2
+
0.9V REFERENCE
-
+
OC1
OC2
-
+
0.9V REFERENCE
+
+
DDR=1
+
1/3
OCSET1
1/32
ISEN1
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO LATCH
VIN
DDR
VCC
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO LATCH
1/32
ISEN2
-
DDR VREF
BUFFER AMP
1/3
OCSET2
-
DDR VTT
REFERENCE
OVER-CURRENT FAULT
OVER-CURRENT FAULT
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