参数资料
型号: ISL6228EVAL3Z
厂商: Intersil
文件页数: 10/16页
文件大小: 0K
描述: EVALUATION BOARD FOR ISL6228
标准包装: 1
系列: Robust Ripple Regulator™ (R³)
主要目的: DC/DC,步降
输出及类型: 2,非隔离
输出电压: 1.5V 或 1.8V,1.8V
电流 - 输出: 8A,8A
输入电压: 3.3 ~ 25 V
稳压器拓扑结构: 降压
频率 - 开关: 270kHz,300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL6228
ISL6228
The ISL6228 monitors the OCSET pin and the VO pin
voltages. Once the OCSET pin voltage is higher than the VO
pin voltage for more than 10μs, the ISL6228 declares an OCP
fault. The value of R OCSET is then written as Equation 6:
the output voltage transversing the V OVR and V OVF
thresholds. The LGATE gate-driver will turn on the low-side
MOSFET to discharge the output voltage, protecting the
load. The LGATE gate-driver will turn off the low-side
R OCSET = ---------------------------
I OC ? DCR
10 μ A
(EQ. 6)
MOSFET once the FB pin voltage is lower than the falling
overvoltage threshold V OVF for more than 2μs. The falling
overvoltage threshold V OVF is typically 106%. That means if
Where:
- R OCSET ( Ω ) is the resistor used to program the
overcurrent setpoint
- I OC is the output current threshold that will activate the
OCP circuit
- DCR is the inductor DC resistance
For example, if I OC is 20A and DCR is 4.5m Ω , the choice of
R OCSET is R OCSET = 20A x 4.5m Ω /10μA = 9k Ω.
Resistor R OCSET and capacitor C SEN form an R-C network
to sense the inductor current. To sense the inductor current
correctly not only in DC operation, but also during dynamic
operation, the R-C network time constant R OCSET C SEN
needs to match the inductor time constant L/DCR. The value
of C SEN is then written as Equation 7:
the FB pin voltage falls below 106% x 0.6V = 0.636V, for
more than 2μs, the LGATE gate-driver will turn off the low-
side MOSFET. If the output voltage rises again, the LGATE
driver will again turn on the low-side MOSFET when the FB
pin voltage is above the rising overvoltage threshold V OVR
for more than 2μs. By doing so, the ISL6228 protects the
load when there is a consistent overvoltage condition.
Undervoltage Protection
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold V UV for more
than 2μs. The FB pin voltage is 0.6V in normal operation.
The undervoltage threshold V UV is typically 86%. That
means if the FB pin voltage is below 86% x 0.6V = 0.516V,
for more than 2μs, an UVP fault is declared, and the
PGOOD pin will pull down to 95 Ω and latch-off the converter.
C SEN = -----------------------------------------
L
R OCSET ? DCR
(EQ. 7)
The fault will remain latched until the EN pin has been pulled
below the falling EN threshold voltage V ENTHF or if V CC has
VCC_THF .
R BOTTOM
V REF = V O ? ---------------------------------------------------
For example, if L is 1.5μH, DCR is 4.5m Ω , and R OCSET is
9k Ω, the choice of C SEN = 1.5μH/(9k Ω x 4.5m Ω ) = 0.037μF .
Upon converter startup, capacitor C SEN initial voltage is 0V.
To prevent false OCP, a 10μA current source flows out of the
VO pin during start up, generating a voltage drop on resistor
R O , which has the same resistance as R OCSET . When
PGOOD pin goes high, the VO pin current source will
terminate.
When an OCP fault is declared, the PGOOD pin will pull
down to 30 Ω and latch off the converter. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage V ENTHF or if V CC has decayed below the
falling POR threshold voltage VVCC_THF .
Overvoltage Protection
The OVP fault detection circuit triggers after the FB pin voltage
is above the rising overvoltage threshold V OVR for more than
2μs. The FB pin voltage is 0.6V in normal operation. The rising
overvoltage threshold V OVR is typically 116%. That means if
the FB pin voltage is above 116% x 0.6V = 0.696V, for more
than 2μs, an OVP fault is declared.
When an OVP fault is declared, the PGOOD pin will pull
down to 60 Ω and latch-off the converter. The OVP fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage V ENTHF or if V CC has decayed
below the falling POR threshold voltage VVCC_THF .
decayed below the falling POR threshold voltage
V
Programming the Output Voltage
When the converter is in regulation there will be 0.6V from
the FB pin to the GND pin. Connect a two-resistor voltage
divider across the VO pin and the GND pin with the output
node connected to the FB pin. Scale the voltage-divider
network such that the FB pin is 0.6V with respect to the GND
pin when the converter is regulating at the desired output
voltage. The output voltage can be programmed from 0.6V
to 5V.
Programming the output voltage is written as Equation 8:
(EQ. 8)
R TOP + R BOTTOM
Where:
- V O is the desired output voltage of the converter
- The voltage to which the converter regulates the FB pin
is the V REF
- R TOP is the voltage-programming resistor that connects
from the FB pin to the converter output. In addition to
setting the output voltage, this resistor is part of the loop
compensation network
- R BOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin
Choose R TOP value first, and calculate R BOTTOM according
to Equation 9:
R BOTTOM = -----------------------------------
Although the converter has latched-off in response to an
OVP fault, the LGATE gate-driver output will retain the ability
to toggle the low-side MOSFET on and off, in response to
10
V REF ? R TOP
V O – V REF
(EQ. 9)
FN9095.2
May 7, 2008
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