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参数资料
| 型号： | ISL6228IRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 28-TQFN |
| 标准包装： | 6,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 频率 - 最大： | 600kHz |
| 电源电压： | 3.3 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6228
( I MAX ? ( D – D ) ) + ? x ? I MAX ? ------ ?
P CON_LS ≈ I LOAD ? r DS ( ON ) _LS ? ( 1 – D )
dissipates heat as a function of RMS current and frequency.
Be sure that I P-P is shared by a sufficient quantity of paralleled
capacitors so that they operate below the maximum rated
RMS current at f SW . Take into account that the rated value of
a capacitor can fade as much as 50% as the DC voltage
across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater
than the maximum input voltage, while a voltage rating of 1.5
times is a preferred rating. Figure 7 is a graph of the input
RMS ripple current, normalized relative to output load current,
as a function of duty cycle that is adjusted for converter
efficiency. The ripple current calculation is written as
Equation 18:
2 2 2 D
? 12 ?
I IN_RMS , NORMALIZED = -----------------------------------------------------------------------------------------------------
I MAX
(EQ. 18)
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum V DS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low gate charge so that the
device spends the least amount of time dissipating power in
the linear region. Unlike the low-side MOSFET which has the
drain-source voltage clamped by its body diode during turn
off, the high-side MOSFET turns off with V IN - V OUT , plus the
spike, across it. The preferred low-side MOSFET
emphasizes low r DS(ON) when fully saturated to minimize
conduction loss.
For the low-side (LS) MOSFET, the power loss can be
assumed to be conductive only and is written as Equation 20:
2
(EQ. 20)
For the high-side (HS) MOSFET, the its conduction loss is
written as Equation 21:
Where:
- I MAX is the maximum continuous I LOAD of the converter
P CON_HS = I LOAD
2
?
r DS ( ON ) _HS ? D
(EQ. 21)
P SW_HS = ----------------------------------------------------------------- + -------------------------------------------------------------
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of I MAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter which is written as:
For the high-side MOSFET, the switching loss is written as
Equation 22:
V IN ? I VALLEY ? t ON ? f SW V IN ? I PEAK ? t OFF ? f SW
2 2
V O
V IN ? EFF
D = --------------------------
(EQ. 19)
Where:
(EQ. 22)
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
0.60
0.55
0.50
0.45
0.40
0.35
- I VALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- I PEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- t ON is the time required to drive the device into
saturation
- t OFF is the time required to drive the device into cut-off
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as
Equation 23:
Δ V BOOT
0.30
0.25
0.20
0.15
x=1
x = 0.75
x = 0.50
x = 0.25
x=0
Q g
C BOOT = ------------------------
Where:
(EQ. 23)
0.10
0.05
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
- Q g is the total gate charge required to turn on the
high-side MOSFET
- Δ V BOOT , is the maximum allowed voltage decay across
DUTY CYCLE
FIGURE 7. NORMALIZED RMS INPUT CURRENT
12
the boot capacitor each time the high-side MOSFET is
switched on
FN9095.2
May 7, 2008
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