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参数资料
| 型号： | ISL6228IRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 8/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 28-TQFN |
| 标准包装： | 6,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 频率 - 最大： | 600kHz |
| 电源电压： | 3.3 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6228
current through C R is provided by a transconductance
amplifier g m that measures the VIN and VO pin voltages.
The positive slope of V R can be written as Equation 1:
Soft-Start Delay t SS begins and the output voltage begins to
rise. The FB pin ramps to 0.6V in approximately 1.5ms and
the PGOOD pin goes to high impedance approximately
V RPOS = ( g m ) ? ( V IN – V OUT ) ? C R
(EQ. 1)
1.25ms after the FB pin voltage reaches 0.6V.
The negative slope of V R can be written as Equation 2:
V RNEG = g m ? V OUT ? C R
(EQ. 2)
1.5ms
Vo
VCC and PVCC
Where g m is the gain of the transconductance amplifier.
A window voltage V W is referenced with respect to the error
amplifier output voltage V COMP , creating an envelope into
which the ripple voltage V R is compared. The amplitude of
V W is set by a resistor connected across the FSET and GND
pins. The V R, V COMP, and V W signals feed into a window
comparator in which V COMP is the lower threshold voltage
and V W is the higher threshold voltage. Figure 2 shows
PWM pulses being generated as V R traverses the V W and
V COMP thresholds. The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of V R; it is inversely proportional to the voltage
between V W and V COMP.
EN
FB
PGOOD
1.25ms
FIGURE 3. SOFT-START SEQUENCE
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an
undefined impedance if V CC has not reached the rising POR
threshold V CCR , or if V CC is below the falling POR threshold
V CCF . The ISL6228 features a unique fault-identification
capability that can drastically reduce trouble-shooting time
and effort. The pull-down resistance of the PGOOD pin
Ripple Capacitor Voltage CR
Window Voltage VW
corresponds to the fault status of the controller. The PGOOD
pull-down resistance is 95 Ω during soft-start or if an UVP
occurs, 30 Ω for an OCP, or 60 Ω for OVP.
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION
PGOOD RESISTANCE
Error Amplifier Voltage VCOMP
PWM
VCC Below POR
Soft-start or Undervoltage
Overvoltage
Overcurrent
Undefined
90 Ω
60 Ω
30 Ω
MOSFET Gate-Drive Outputs LGATE and UGATE
FIGURE 2. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
Power-On Reset
The ISL6228 is disabled until the voltage at the VCC pin has
increased above the rising power-on reset (POR) V CCR
threshold voltage. The controller will be disabled when the
voltage at the VCC pin decreases below the falling POR
V CCF threshold voltage.
EN, Soft-Start and PGOOD
The ISL6228 uses a digital soft-start circuit to ramp the
output voltage of the converter to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the in-rush
current through the output capacitors as they charge to the
desired regulation voltage. When the EN pin is pulled above
the rising EN threshold voltage V ENTHR , the PGOOD
8
The ISL6228 has internal gate-drivers for the high-side and
low-side N-Channel MOSFETs. The low-side gate-drivers
are optimized for low duty-cycle applications where the low-
side MOSFET conduction losses are dominant, requiring a
low r DS(ON) MOSFET. The LGATE pull-down resistance is
small in order to clamp the gate of the MOSFET below the
V GS(th) at turnoff. The current transient through the gate at
turn-off can be considerable because the gate charge of a
low r DS(ON) MOSFET can be large. Adaptive shoot-through
protection prevents a gate-driver output from turning on until
the opposite gate-driver output has fallen below
approximately 1V. The dead-time shown in Figure 4 is
extended by the additional period that the falling gate voltage
stays above the 1V threshold. The typical dead-time is 21ns.
The high-side gate-driver output voltage is measured across
the UGATE and PHASE pins while the low-side gate-driver
output voltage is measured across the LGATE and PGND
FN9095.2
May 7, 2008
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