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参数资料
| 型号： | ISL6228LOEVAL3Z |
| 厂商： | Intersil |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL6228LO |
| 标准包装： | 1 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 1.5V 或 1.8V，1.8V |
| 电流 - 输出： | 8A，8A |
| 输入电压： | 3.3 ~ 25 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 270kHz，300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL6228 |
ISL6228
Programming the PWM Switching Frequency
The ISL6228 does not use a clock signal to produce PWMs.
The PWM switching frequency f SW is programmed by the
resistor R FSET that is connected from the FSET pin to the
GND pin. The approximate PWM switching frequency is
written as Equation 10:
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a single-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following section. In addition to this guide, Intersil provides
f SW = ---------------------------
1
K ? R FSET
(EQ. 10)
complete reference designs that include schematics, bills of
materials, and example board layouts.
(EQ. 11)
R FSET = ------------------
Estimating the value of R FSET is written as Equation 11:
1
K ? f SW
Where:
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as
Equation 13:
V O
- f SW is the PWM switching frequency
- R FSET is the f SW programming resistor
- K = 1.5 x 10 -10
D = ---------
V IN
(EQ. 13)
V O ? ( 1 – D )
I PP = ------------------------------
(EQ. 15)
P COPPER = I LOAD
It is recommended that whenever the control loop
compensation network is modified, f SW should be checked
for the correct frequency and if necessary, adjust R FSET .
Compensation Design
Figure 6 shows the recommended Type-II compensation
circuit. The FB pin is the inverting input of the error amplifier.
The COMP signal, the output of the error amplifier, is inside the
chip and unavailable to users. C INT is a 100pF capacitor
integrated inside the IC, connecting across the FB pin and the
COMP signal. R TOP , R FB , C FB and C INT form the Type-II
compensator. The frequency domain transfer function is given
The output inductor peak-to-peak ripple current is written as
Equation 14:
(EQ. 14)
f SW ? L
A typical step-down DC/DC converter will have an I P-P of
20% to 40% of the maximum DC output load current. The
value of I PP is selected based upon several criteria such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated by Equation 15:
2
? DCR
G COMP ( s ) = -------------------------------------------------------------------------------------------
s ? R TOP ? C INT ? ( 1 + s ? R FB ? C
by Equation 12:
1 + s ? ( R TOP + R FB ) ? C FB
FB
)
(EQ. 12)
Where I LOAD is the converter output DC current.
The copper loss can be significant so attention has to be
given to the DCR selection. Another factor to consider when
choosing the inductor is its saturation characteristics at
elevated temperature. A saturated inductor could cause
C INT = 100pF
R FB
C FB
destruction of circuit components, as well as nuisance OCP
faults.
-
FB
R TOP
VO
A DC/DC buck regulator must have output capacitance C O
into which ripple current I P-P can flow. Current I PP develops
a corresponding ripple voltage V P-P across C O, which is the
EA
sum of the voltage drop across the capacitor ESR and of the
COMP
+
R BOTTOM
voltage change stemming from charge moved in and out of
the capacitor. These two voltages are written as
Equation 16:
REF
Δ V C = -----------------------------
ISL6228
FIGURE 6. COMPENSATION REFERENCE CIRCUIT
The LC output filter has a double pole at its resonant frequency
that causes rapid phase change. The R 3 modulator used in the
Δ V ESR = I P-P ? E SR
and Equation 17:
I P-P
8 ? C O ? f SW
(EQ. 16)
(EQ. 17)
ISL6228 makes the LC output filter resemble a first order
system in which the closed loop stability can be achieved with
the recommended Type-II compensation network. Intersil
provides a PC-based tool (example page is shown later) that
can be used to calculate compensation network component
values and help simulate the loop frequency response.
11
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required V P-P is achieved.
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors should be considered. A capacitor
FN9095.2
May 7, 2008
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