参数资料
| 型号： | ISL6237IRZ |
| 厂商： | Intersil |
| 文件页数： | 32/35页 |
| 文件大小： | 0K |
| 描述： | IC MAIN PWR CTRLR QUAD 32-QFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 60 |
| 应用： | 控制器，笔记本电脑电源系统 |
| 输入电压： | 5.5 V ~ 25 V |
| 输出数： | 4 |
| 输出电压： | 多重 |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
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ISL6237
When using low-capacity filter capacitors such as polymer
types, capacitor size is usually determined by the capacity
required to prevent VSAG and VSOAR from tripping the
undervoltage and overvoltage fault latches during load
transients in ultrasonic mode.
For low input-to-output voltage differentials (V IN / V OUT < 2),
additional output capacitance is required to maintain stability
and good efficiency in ultrasonic mode. The amount of
overshoot due to stored inductor energy can be calculated as:
Choose a synchronous rectifier (Q 2 /Q 4 ) with the lowest
possible r DS(ON) . Ensure the gate is not pulled up by the
high-side switch turning on due to parasitic drain-to-gate
capacitance, causing cross-conduction problems. Switching
losses are not an issue for the synchronous rectifier in the
buck topology since it is a zero-voltage switched device
when using the buck topology.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty-factor
I PEAK ? L
2 ? C OUT ? V OUT_
2
V SOAR = ------------------------------------------------
(EQ. 16)
extremes. For the high-side MOSFET, the worst-case power
dissipation (PD) due to the MOSFET's r DS(ON) occurs at the
minimum battery voltage:
PD ( Q H Resistance ) = ? ------------------------ ? ( I LOAD ) ? r DS ( ON )
where I PEAK is the peak inductor current.
Input Capacitor Selection
? V OUT _ ? 2
? V IN ( MIN ) ?
(EQ. 18)
The input capacitors must meet the input-ripple-current
(I RMS ) requirement imposed by the switching current. The
ISL6237 dual switching regulator operates at different
frequencies. This interleaves the current pulses drawn by
the two switches and reduces the overlap time where they
add together. The input RMS current is much smaller in
comparison than with both SMPSs operating in phase. The
input RMS current varies with load and the input voltage.
The maximum input capacitor RMS current for a single
SMPS is given by:
Generally, a small high-side MOSFET reduces switching
losses at high input voltage. However, the r DS(ON) required
to stay within package power-dissipation limits often limits
how small the MOSFET can be. The optimum situation
occurs when the switching (AC) losses equal the conduction
(r DS(ON) ) losses.
Switching losses in the high-side MOSFET can become an
insidious heat problem when maximum battery voltage is
applied, due to the squared term in the CV 2 f switching-loss
equation. Reconsider the high-side MOSFET chosen for
? V OUT ( V IN – V OUT _ ) ?
I RMS ≈ I LOAD ? ?
? V IN ?
------------------------------------------------------------
(EQ. 17)
adequate r DS(ON) at low battery voltages if it becomes
extraordinarily hot when subjected to V IN(MAX) .
PD ( Q H Switching ) = ( V IN ( MAX ) ) ? ?
2 ? C RSS ? f SW ? I LOAD ?
PD ( Q L ) = ? ? I LOAD ? r DS ( ON )
When V IN = 2 ? V OUT _ ( D = 50% ) , IRMS has maximum
current of I LOAD ? 2 .
The ESR of the input-capacitor is important for determining
capacitor power dissipation. All the power (I RMS2 x ESR)
heats up the capacitor and reduces efficiency. Nontantalum
chemistries (ceramic or OS-CON) are preferred due to their
low ESR and resilience to power-up surge currents. Choose
input capacitors that exhibit less than +10°C temperature
rise at the RMS input current for optimal circuit longevity.
Place the drains of the high-side switches close to each
other to share common input bypass capacitors.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability (>5A)
when using high-voltage (>20V) AC adapters. Low-current
applications usually require less attention.
Choose a high-side MOSFET (Q 1 /Q 3 ) that has conduction
losses equal to the switching losses at the typical battery
voltage for maximum efficiency. Ensure that the conduction
losses at the minimum input voltage do not exceed the
package thermal limits or violate the overall thermal budget.
Ensure that conduction losses plus switching losses at the
maximum input voltage do not exceed the package ratings
or violate the overall thermal budget.
32
Calculating the power dissipation in NH (Q 1 /Q 3 ) due to
switching losses is difficult since it must allow for quantifying
factors that influence the turn-on and turn-off times. These
factors include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PC board layout
characteristics. The following switching-loss calculation
provides only a very rough estimate and is no substitute for
bench evaluation, preferably including verification using a
thermocouple mounted on NH (Q 1 /Q 3 ):
-----------------------------------------------------
? I GATE ?
(EQ. 19)
where C RSS is the reverse transfer capacitance of Q H
(Q 1 /Q 3 ) and I GATE is the peak gate-drive source/sink
current.
For the synchronous rectifier, the worst-case power
dissipation always occurs at maximum battery voltage:
? V OUT ? 2
1 – -------------------------- (EQ. 20)
? V IN ( MAX ) ?
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I LOAD(MAX) but are not quite high enough to exceed the
FN6418.4
March 18, 2008
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