参数资料
| 型号： | ISL6237IRZ |
| 厂商： | Intersil |
| 文件页数： | 8/35页 |
| 文件大小： | 0K |
| 描述： | IC MAIN PWR CTRLR QUAD 32-QFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 60 |
| 应用： | 控制器，笔记本电脑电源系统 |
| 输入电压： | 5.5 V ~ 25 V |
| 输出数： | 4 |
| 输出电压： | 多重 |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
ISL6237
Pin Descriptions (Continued)
PIN
23
24
25
26
27
28
29
30
31
32
NAME
LGATE2
BOOT2
PHASE2
UGATE2
EN2
POK2
SKIP
OUT2
ILIM2
REFIN2
FUNCTION
SMPS2 Synchronous-Rectifier Gate-Drive Output. LGATE2 swings between GND and PVCC.
Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor according to the “Typical Application
Circuits” starting on page 21 (Figures 62, 63 and 64) See “MOSFET Gate Drivers (UGATE_, LGATE_)” on page 28 .
Inductor Connection for SMPS2. PHASE2 is the internal lower supply rail for the UGATE2 high-side gate driver.
PHASE2 is the current-sense input for the SMPS2.
High-Side MOSFET Floating Gate-Driver Output for SMPS2. UGATE1 swings between PHASE2 and BOOT2.
SMPS2 Enable Input. The SMPS2 is enabled if EN2 is greater than the logic high level and disabled if EN2 is less than
the logic low level. If EN2 is connected to REF, the SMPS2 starts after the SMPS1 reaches regulation (delay start).
Drive EN2 below 0.8V to clear fault level and reset the fault latches.
SMP2 Power-Good Open-Drain Output. POK2 is low when the SMPS2 output voltage is more than 10% below the
normal regulation point or during soft-start. POK2 is high impedance when the output is in regulation and the soft-start
circuit has terminated. POK2 is low in shutdown.
Low-Noise Mode Control. Connect SKIP to GND for normal Idle-Mode (pulse-skipping) operation or to VCC for PWM
mode (fixed frequency). Connect to REF or leave floating for ultrasonic skip mode operation.
SMPS2 Output Voltage-Sense Input. Connect to the SMPS2 output. OUT2 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS2 feedback input in fixed-voltage mode.
SMPS2 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM2 over
a 0.2V to 2V range. There is an internal 5μA current source from VCC to ILIM2. Connect ILIM2 to REF for a fixed
200mV. The logic current limit threshold is default to 100mV value if ILIM2 is higher than VCC - 1V.
Output voltage control for SMPS2. Connect REFIN2 to VCC for fixed 3.3V. Connect REFIN2 to a 3.3V supply for fixed
1.05V. REFIN2 can be used to program SMPS2 output voltage from 0.5V to 2.50V. SMPS2 output voltage is 0V if
REFIN2 < 0.5V.
Typical Performance Curves
Circuit of Figures 62, 63 and 64, no load on LDO, OUT1, OUT2, and REF, V IN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, V EN_LDO = 5V, T A = -40°C to +100°C, unless
otherwise noted. Typical values are at T A = +25°C.
100
7 V IN SKIP MODE
7 V IN PWM MODE
7 V IN ULTRA SKIP MODE
12 V IN SKIP MODE
12 V IN PWM MODE
12 V IN ULTRA SKIP MODE
25 V IN SKIP MODE
25 V IN PWM MODE
25 V IN ULTRA SKIP MODE
100
7 V IN SKIP MODE
7 V IN PWM MODE
7 V IN ULTRA SKIP MODE
12 V IN SKIP MODE
12 V IN PWM MODE
12 V IN ULTRA SKIP MODE
25 V IN SKIP MODE
25 V IN PWM MODE
25 V IN ULTRA SKIP MODE
90
80
70
60
50
40
30
20
10
90
80
70
60
50
40
30
20
10
0
0.001
0.010
0.100
1.000
10.000
0
0.001
0.010
0.100
1.000
10.000
OUTPUT LOAD (A)
FIGURE 1. V OUT2 = 1.05V EFFICIENCY vs LOAD (300kHz)
8
OUTPUT LOAD (A)
FIGURE 2. V OUT1 = 1.5V EFFICIENCY vs LOAD (200kHz)
FN6418.4
March 18, 2008
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