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参数资料
| 型号： | ISL62391HRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 16/21页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CONTROLLER 28TQFN |
| 标准包装： | 6,000 |
| 应用： | 电源控制器 |
| 电源电压： | 5.5 V ~ 25 V |
| 电流 - 电源： | 150µA |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（4x4） |
| 包装： | 带卷 (TR) |
ISL62391, ISL62392, ISL62391C, ISL62392C
Where:
- R OCSET ( Ω ) is the resistor used to program the
overcurrent setpoint
- I OC is the output current threshold that will activate the
OCP circuit
- DCR is the inductor DC resistance
For example, if I OC is 20A and DCR is 4.5m Ω , the choice of
R OCSET is R OCSET = 20A x 4.5m Ω /10μA = 9k Ω.
Resistor R OCSET and capacitor C SEN form an R-C network
to sense the inductor current. To sense the inductor current
correctly, not only in DC operation but also during dynamic
operation, the R-C network time constant R OCSET -C SEN
needs to match the inductor time constant L/DCR. The value
of C SEN is then written as Equation 10:
latched until the EN pin has been pulled below the falling EN
threshold voltage, or until V IN has decayed below the falling
POR threshold. During the latch condition, the ISL62391 and
ISL62391C will tri-state the PHASE node by turning both
UGATE and LGATE off until the latch is cleared.
Although latched, the ISL62392 and ISL62392C LGATE gate-
driver output will retain the ability to toggle the low-side
MOSFET on and off in response to the output voltage
transversing the OVP rising and falling thresholds. The
LGATE gate-driver will turn on the low-side MOSFET to
discharge the output voltage, thus protecting the load from
potentially damaging voltage levels. The LGATE gate-driver
will turn off the low-side MOSFET once the FB pin voltage is
lower than the falling overvoltage threshold for more than 2μs.
The falling overvoltage threshold is typically 106% of the
C SEN = -----------------------------------------
L
R OCSET ? DCR
(EQ. 10)
reference voltage, or 1.06*0.6V = 0.636V. This soft-crowbar
process repeats as long as the output voltage fault is present,
For example, if L is 1.5μH, DCR is 4.5m Ω , and R OCSET is
9k Ω, the choice of C SEN = 1.5μH/(9k Ω x 4.5m Ω ) = 0.037μF .
Upon converter start-up, the C SEN capacitor bias is 0V. To
prevent false OCP during this time, a 10μA current source
flows out of the ISEN1 pin, generating a voltage drop on the
R O resistor, which should be chosen to have the same
resistance as R OCSET . When the PGOOD pin goes high, the
ISEN1 pin current source will be removed.
When an OCP fault is declared, the PGOOD pin will pull-down
to 32 Ω and latch-off the converter. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage, or until V IN has decayed below the falling
POR threshold.
When using a discrete current sense resistor, inductor
time-constant matching is not required. Equation 7 remains
unchanged, but Equation 8 is modified in Equation 11:
allowing the ISL62392 and ISL62392C to protect against
persistent overvoltage conditions.
Undervoltage Protection
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold for more than
2μs. The undervoltage threshold is typically 86% of the
reference voltage, or 0.86*0.6V = 0.516V. If a UVP fault is
declared, the PGOOD pin will pull-down with 32 Ω and latch-off
the converter. The fault will remain latched until the EN pin
has been pulled below the falling enable threshold, or if V IN
has decayed below the falling POR threshold.
Programming the Output Voltage
When the converter is in regulation, there will be 0.6V
between the FB and GND pins. Connect a two-resistor
voltage divider across the OUT and GND pins with the
output node connected to the FB pin, as shown in Figure 27.
Scale the voltage-divider network such that the FB pin is
V OCSET1 – V ISEN1 = I L ? R SENSE – 10 μ A ? R OCSET
(EQ. 11)
0.6V with respect to the GND pin when the converter is
regulating at the desired output voltage. The output voltage
I OC ? R SENSE
R OCSET = -------------------------------------
10 μ A
V OUT = V REF ? ? 1 + ----------------------------- ?
Furthermore, Equation 9 is changed in Equation 12:
(EQ. 12)
Where R SENSE is the series power resistor for sensing
inductor current. For example, with an R SENSE = 1m Ω and
an OCP target of 10A, R OCSET = 1k Ω.
Overvoltage Protection
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold for more
than 2μs. The FB pin voltage is 0.6V in normal operation.
The rising overvoltage threshold is typically 116% of that
value, or 1.16*0.6V = 0.696V.
For ISL62391, ISL62392, ISL62391C and ISL62392C, when
an OVP fault is declared, the PGOOD pin will pull-down with
32 Ω and latch-off the converter. The OVP fault will remain
16
can be programmed from 0.6V to 5.5V.
Programming the output voltage is written as Equation 13:
? R TOP ?
(EQ. 13)
? R BOTTOM ?
Where:
- V OUT is the desired output voltage of the converter
- The voltage to which the converter regulates the FB pin
is the V REF (0.6V)
- R TOP is the voltage-programming resistor that connects
from the FB pin to the converter output. In addition to
setting the output voltage, this resistor is part of the loop
compensation network
- R BOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin
Choose R TOP first when compensating the control loop, and
then calculate R BOTTOM according to Equation 14:
FN6666.7
August 22, 2013
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