参数资料
| 型号： | ISL6262CRZ-TK |
| 厂商： | Intersil |
| 文件页数： | 19/27页 |
| 文件大小： | 0K |
| 描述： | IC CORE CTRLR 2PHASE 48-QFN |
| 标准包装： | 1,000 |
| 应用： | 转换器，Intel IMVP-6 |
| 输入电压： | 5 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.3 V ~ 1.5 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6262
SLEWRATE, as given in the IMVP-6 specification will
determine the choice of the SOFT capacitor, C SOFT , by the
IMVP-6_PWRGD signal. This timer allows IMVP-6_PWRGD
to go high approximately 6.8ms after CLK_EN# goes low.
C SOFT = ------------------------------------
following equation:
I GV
SLEWRATE
(EQ. 1)
Static Mode of Operation - Processor Die Sensing
Die sensing is the ability of the controller to regulate the core
output voltage at a remotely sensed point. This allows the
Using a SLEWRATE of 10mV/μs, and the typical I GV value,
given in the Electrical Specification Table of 200μA, C SOFT
is
voltage regulator to compensate for various resistive drops
in the power path and ensure that the voltage seen at the
CPU die is the correct level independent of load current.
C SOFT = 200 μ A ? ( 10mV ? 1 μ s )
(EQ. 2)
The VSEN and RTN pins of the ISL6262 are connected to
Kelvin sense leads at the die of the processor through the
A choice of 0.015μF would guarantee a SLEWRATE of
10mV/μs is met for minimum I GV value, given in the
Electrical Specification Table. This choice of C SOFT will then
control the Start-Up slewrate as well. One should expect the
output voltage to slew to the Boot value of 1.2V at a rate
given by the following equation:
processor socket. These signal names are Vcc_sense and
Vss_sense respectively. This allows the voltage regulator to
tightly control the processor voltage at the die, independent
of layout inconsistencies and voltage drops. This Kelvin
sense technique provides for extremely tight load line
regulation.
dV I SS 41 μ A
0.015 μ F
C SOFT
------- = ------------------- = ----------------------- = 2.8mV ? μ s
dt
(EQ. 3)
These traces should be laid out as noise sensitive traces.
For optimum load line regulation performance, the traces
Selecting RBIAS
To properly bias the ISL6262, a reference current is
established by placing a 147k Ω , 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate,
10μA current source from which OCSET reference current
can be derived.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality signal
ground is connected to the opposite side of the RBIAS
resistor. Do not connect any other components to this pin as
this would negatively impact performance. Capacitance on
this pin would create instabilities and should be avoided.
Start-Up Operation - CLK_EN# and PGOOD
The ISL6262 provides a 3.3V logic output pin for CLK_EN#.
The 3V3 pin allows for a system 3.3V source to be
connected to separated circuitry inside the ISL6262, solely
devoted to the CLK_EN# function. The output is a 3.3V
CMOS signal with 4mA sourcing and sinking capability. This
implementation removes the need for an external pull-up
resistor on this pin, and due to the normal level of this signal
being a low, removes the leakage path from the 3.3V supply
to ground through the pull-up resistor. This reduces 3.3V
supply current, that would occur under normal operation with
a pull-up resistor, and prolongs battery life. The 3.3V supply
should be decoupled to digital ground, not to analog ground
for noise immunity.
As mentioned in the “Theory of Operation” section of this
datasheet, CLK_EN# is logic level high at start-up until 20μs
after the system Vccp and Vcc_mch supplies are within
regulation, and the Vcc-core is in regulation at the Boot level.
Approximately 20μs after these voltages are within
regulation, as indicated by PGD_IN going high, CLK_EN#
goes low, triggering an internal timer for the
19
connecting these two pins to the Kelvin sense leads of the
processor must be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. To achieve
optimum performance, place common mode and differential
mode RC filters to analog ground on VSEN and RTN as
shown in Figure 31. The filter resistors should be 10 Ω so that
they do not interact with the 50k Ω input resistance of the
differential amplifier. The filter resistor may be inserted
between Vcc_sense and VSEN pin. Another option is to
place to the filter resistor between Vcc_sense and VSEN pin
and between Vss_sense and RTN pin. Whether to need
these RC filter really depends on the actual board layout and
noise environment.
Due to the fact that the voltage feedback to the switching
regulator is sensed at the processor die, there exists the
potential of an overvoltage due to an open circuited
feedback signal, should the regulator be operated without
the processor installed. Due to this fact, we recommend the
use of the Ropn1 and Ropn2 connected to Vout and ground
as shown in Figure 31. These resistors will provide voltage
feedback in the event that the system is powered up without
a processor installed. These resistors may typically range
from 20 to 100 Ω .
FN9199.2
May 15, 2006
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6262CRZ-TR5242 | 制造商:Intersil Corporation 功能描述:53350B01 MASK ONLY AND DOT ON BRAND - Tape and Reel |
| ISL6262IRZ | 功能描述:直流/直流开关调节器 TWO-PHS DC/DC BUCK CNTRLR IMVP-6 4 8LD RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| ISL6262IRZ-T | 功能描述:直流/直流开关调节器 TWO-PHS DC/DC BUCK CNTRLR IMVP-6 4 8LD RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| ISL6263 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:5-Bit VID Single-Phase Voltage Regulator for IMVP-6 Santa Rosa GPU Core |
| ISL6263A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:5-Bit VID Single-Phase Voltage Regulator with Power Monitor for IMVP-6 Santa Rosa GPU Core |
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