参数资料
型号: ISL6263ACRZ
厂商: Intersil
文件页数: 10/19页
文件大小: 0K
描述: IC VREG 5BIT 1PHASE 32-QFN
标准包装: 60
应用: 转换器,Intel IMVP-6
输入电压: 5 V ~ 25 V
输出数: 1
输出电压: 0.41 V ~ 1.29 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 管件
ISL6263A
TABLE 2. VID TABLE FOR INTEL IMVP-6+ V CCGFX CORE
Theory of Operation
VID4
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
x
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
x
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V CCGFX
(V)
0
1.28750
1.26175
1.23600
1.21025
1.18450
1.15875
1.13300
1.10725
1.08150
1.05575
1.03000
1.00425
0.97850
0.95275
0.92700
0.90125
0.87550
0.84975
0.82400
0.79825
0.77250
0.74675
0.72100
0.69525
0.66950
0.64375
0.61800
0.59225
0.56650
0.54075
0.51500
0.41200
The R 3 Modulator
The heart of the ISL6263A is Intersil’s Robust-Ripple-
Regulator (R 3 ) Technology?. The R 3 modulator is a hybrid
of fixed frequency PWM control, and variable frequency
hysteretic control that will simultaneously affect the PWM
switching frequency and PWM duty cycle in response to
input voltage and output load transients.
The term “Ripple” in the name “Robust-Ripple-Regulator”
refers to the synthesized voltage-ripple signal V R that
appears across the internal ripple-capacitor C R. The V R
signal is a representation of the output inductor ripple
current. Transconductance amplifiers measuring the input
voltage of the converter and the output set-point voltage
V SOFT , together produce the voltage-ripple signal V R .
A voltage window signal V W is created across the VW and
COMP pins by sourcing a current proportional to g m V soft
through a parallel network consisting of resistor R FSET and
capacitor C FSET. The synthesized voltage-ripple signal V R
along with similar companion signals are converted into
PWM pulses.
The PWM frequency is proportional to the difference in
amplitude between V W and V COMP . Operating on these
large-amplitude, low noise synthesized signals allows the
ISL6263A to achieve lower output ripple and lower phase
jitter than either conventional hysteretic or fixed frequency
PWM controllers. Unlike conventional hysteretic converters,
the ISL6263A has an error amplifier that allows the controller
to maintain tight voltage regulation accuracy throughout the
VID range from 0.41200V to 1.28750V.
Power-On Reset
The ISL6263A is disabled until the voltage at the VDD pin
has increased above the rising VDD power-on reset (POR)
V DD_THR threshold voltage. The controller will become
disabled when the voltage at the VDD pin decreases below
the falling POR V DD_THF threshold voltage.
Start-Up Timing
Figure 4 shows the ISL6263A start-up timing. Once VDD has
ramped above V DD_THR , the controller can be enabled by
pulling the VR_ON pin voltage above the input-high
threshold V VR_ONH . Approximately 100μs later, the soft-start
capacitor C SOFT begins slewing to the designated VID
set-point as it is charged by the soft-start current source I SS .
The V CCGFX output voltage of the converter follows the
V SOFT voltage ramp to within 10% of the VID set-point then
counts 13 switching cycles, then changes the open-drain
output of the PGOOD pin to high impedance. During
soft-start, the regulator always operates in continuous
conduction mode (CCM).
10
FN9284.3
July 8, 2010
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