参数资料
型号: ISL6263ACRZ
厂商: Intersil
文件页数: 13/19页
文件大小: 0K
描述: IC VREG 5BIT 1PHASE 32-QFN
标准包装: 60
应用: 转换器,Intel IMVP-6
输入电压: 5 V ~ 25 V
输出数: 1
输出电压: 0.41 V ~ 1.29 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 管件
ISL6263A
TABLE 3. FAULT PROTECTION SUMMARY OF ISL6263A
A severe overvoltage protection fault occurs immediately
FAULT
DURATION
PRIOR TO
PROTECTION
FAULT
after the voltage between the VO and VSS pins exceed the
rising severe-overvoltage threshold V OVPS , which is 1.545V,
the same reference voltage used by the VID DAC. The
FAULT TYPE
PROTECTION
ACTIONS
RESET
ISL6263A will latch UGATE and PGOOD low but unlike other
Overcurrent
Short Circuit
Overvoltage
(+195mV)
between VO pin
and SOFT pin
Severe
Overvoltage
(+1.55V)
between VO pin
and VSS pin
Undervoltage
(-300mV)
between VO pin
and SOFT pin
120μs
<2μs
1ms
Immediately
1ms
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
UGATE, and Cycle
PGOOD latched low, VDD only
LGATE toggles ON
when VO >1.55V
OFF when
VO <0.77V
until fault reset
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
protective faults, LGATE remains high until the voltage
between VO and VSS falls below approximately 0.77V, at
which time LGATE is pulled low. The LGATE pin will continue
to switch high and low at 1.545V and 0.77V until VDD has
gone below the falling POR threshold voltage VVDD_THF.
This provides maximum protection against a shorted
high-side MOSFET while preventing the output voltage from
ringing below ground. The severe-overvoltage fault circuit
can be triggered after another fault has already been
latched.
Gate-Driver Outputs LGATE and UGATE
The ISL6263A has internal high-side and low-side
N-Channel MOSFET gate-drivers. The LGATE driver is
optimized for low duty-cycle applications where the low-side
MOSFET conduction losses are dominant. The LGATE
pull-down resistance is very low in order to clamp the
gate-source voltage of the MOSFET below the V GS(th) at
turnoff. The current transient through the low-side gate at
turnoff can be considerable due to the characteristic large
switching charge of a low r DS(ON) MOSFET.
Adaptive shoot-through protection prevents the gate-driver
PWM
outputs from going high until the opposite gate-driver output
has fallen below approximately 1V. The UGATE turn-on
LGATE
UGATE
t PDRU t PDRL
FIGURE 6. GATE DRIVER TIMING DIAGRAM
2.0
1.8
1.6
1.4
1.2
1.0
1V
1V
propagation delay t PDRU and LGATE turn-on propagation
delay t PDRL are found in the “Electrical Specifications ” table
on page 7. The power for the LGATE gate-driver is sourced
directly from the PVCC pin. The power for the UGATE
gate-driver is sourced from a boot-strap capacitor connected
across the BOOT and PHASE pins. The boot capacitor is
charged from PVCC through an internal boot-strap diode
each time the low-side MOSFET turns on, pulling the
PHASE pin low.
Internal Bootstrap Diode
The ISL6263A has an integrated boot-strap Schottky diode
connected from the PVCC pin to the BOOT pin. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit.
The minimum value of the bootstrap capacitor can be
calculated from Equation 3:
C BOOT ≥ ------------------------
0.8
0.6
0.4
Q GATE = 100n C
Q GATE
Δ V BOOT
(EQ. 3)
0.2 20nC
0.0
0.0 0.1
0.2
0.3
0.4 0.5 0.6
Δ V BOOT_CAP (V)
0.7
0.8 0.9
1.0
where Q GATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The Δ V BOOT term is
defined as the allowable droop in the rail of the upper drive.
FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
13
As an example, suppose an upper MOSFET has a gate
charge, Q GATE , of 25nC at 5V and also assume the droop in
FN9284.3
July 8, 2010
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