参数资料
| 型号： | ISL6263DHRZ |
| 厂商： | Intersil |
| 文件页数： | 12/17页 |
| 文件大小： | 0K |
| 描述： | IC VREG 3BIT 1PHASE 32-QFN |
| 标准包装： | 60 |
| 应用： | 转换器，GPU 内核电源 |
| 输入电压： | 5 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.7 V ~ 1.09 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 管件 |
ISL6263D
below the falling POR threshold voltage VVDD_THF. This
provides maximum protection against a shorted high-side
MOSFET while preventing the output voltage from ringing
below ground. The severe-overvoltage fault circuit can be
triggered after another fault has already been latched.
Gate-Driver Outputs LGATE and UGATE
The ISL6263D has internal high-side and low-side
N-Channel MOSFET gate-drivers. The LGATE driver is
optimized for low duty-cycle applications where the low-side
MOSFET conduction losses are dominant. The LGATE
pull-down resistance is very low in order to clamp the
gate-source voltage of the MOSFET below the V GS(th) at
turn-off. The current transient through the low-side gate at
turn-off can be considerable due to the characteristic large
switching charge of a low r DS(ON) MOSFET.
PWM
across the BOOT and PHASE pins. The boot capacitor is
charged from PVCC through an internal bootstrap diode
each time the low-side MOSFET turns on, pulling the
PHASE pin low.
Internal Bootstrap Diode
The ISL6263D has an integrated boot-strap Schottky diode
connected from the PVCC pin to the BOOT pin. Simply adding
an external capacitor across the BOOT and PHASE pins
completes the bootstrap circuit.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
Q GATE = 100nC
20nC
LGATE
1V
0.2
0.0
0.0 0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
UGATE
1V
Δ V BOOT_CAP (V)
FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
t PDRU
t PDRL
The minimum value of the bootstrap capacitor can be
FIGURE 6. GATE DRIVER TIMING DIAGRAM
calculated using Equation 3:
C BOOT ≥ ------------------------
Adaptive shoot-through protection prevents the gate-driver
outputs from going high until the opposite gate-driver output
Q GATE
Δ V BOOT
(EQ. 3)
has fallen below approximately 1V. The UGATE turn-on
propagation delay t PDRU and LGATE turn-on propagation
delay t PDRL are found in the “Electrical Specifications” table
on page 6. The power for the LGATE gate-driver is sourced
where Q GATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The Δ V BOOT term is
defined as the allowable droop in the rail of the upper drive.
directly from the PVCC pin. The power for the UGATE
gate-driver is sourced from a bootstrap capacitor connected
TABLE 3. FAULT PROTECTION SUMMARY OF ISL6263D
FAULT DURATION
FAULT TYPE
Overcurrent
Short Circuit
Overvoltage (+195mV) between VO
PRIOR TO PROTECTION
120μs
<2μs
1ms
PROTECTION ACTIONS
LGATE, UGATE, and PGOOD latched low
LGATE, UGATE, and PGOOD latched low
LGATE, UGATE, and PGOOD latched low
FAULT RESET
Cycle VR_ON or VDD
Cycle VR_ON or VDD
Cycle VR_ON or VDD
pin and SOFT pin
Severe Overvoltage (+1.55V) between
VO pin and VSS pin
Immediately
UGATE, and PGOOD latched low, LGATE
toggles ON when VO>1.55V OFF when VO
Cycle VDD only
<0.76V until fault reset
Undervoltage (-300mV) between VO
1ms
LGATE, UGATE, and PGOOD latched low
Cycle VR_ON or VDD
pin and SOFT pin
12
FN6753.1
July 8, 2010
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相关代理商/技术参数 |
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| ISL6263DHRZ-T | 功能描述:IC VREG 3BIT 1PHASE 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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| ISL6264CRZ-T | 功能描述:IC CORE CTRLR TWO-PHASE 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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