参数资料
| 型号： | ISL6265CHRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 14/27页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR MULTI-OUTPUT 48TQFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI 兼容移动式 CPU |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 3 |
| 输出电压： | 0.5 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
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ISL6265C
Theory of Operation
The ISL6265C is a flexible multi-output controller supporting
Northbridge and single or dual power planes required by Class M
AMD Mobile CPUs. In single plane applications, both core voltage
regulators operate single-phase. In uniplane core applications,
the core voltage regulators are configured to operate as a
two-phase regulator. All three regulator outputs include
integrated gate drivers for reduced system cost and small board
area. The regulators provide optimum steady-state and transient
performance for microprocessor applications. System efficiency
is enhanced by idling a phase in uniplane configurations at low-
current and implementing automatic DCM-mode operation when
PSI_L is asserted to logic low.
A window voltage V W is referenced with respect to the error
amplifier output voltage V COMP , creating an envelope into which
the ripple voltage V R is compared. The amplitude of V W is set by a
resistor connected across the FSET and GND pins. The V R, V COMP,
and V W signals feed into a window comparator in which V COMP is
the lower threshold voltage and V W is the higher threshold
voltage. Figure 7 shows PWM pulses being generated as V R
traverses the V W and V COMP thresholds. The PWM switching
frequency is proportional to the slew rates of the positive and
negative slopes of V R; it is inversely proportional to the voltage
between V W and V COMP .
VIN
V W
C R TO
PWM
PWM
The heart of the ISL6265C is the R 3 Technology?, Intersil's
Robust Ripple Regulator modulator. The R 3 modulator combines
the best features of fixed frequency PWM and hysteretic PWM
while eliminating many of their shortcomings. The ISL6265C
modulator internally synthesizes an analog of the inductor ripple
current and uses hysteretic comparators on those signals to
establish PWM pulse widths. Operating on these large-
amplitude, noise-free synthesized signals allows the ISL6265C to
achieve lower output ripple and lower phase jitter than either
conventional hysteretic or fixed frequency PWM controllers.
Unlike conventional hysteretic converters, the ISL6265C has an
VO
+
g m V IN
+
g m V O
PWM FREQUENCY
CONTROL
+
-
V R
+ V COMP
-
CONTROL
+
+
R
Q
S
ISL6265C
FSET
error amplifier that allows the controller to maintain a 0.5%
voltage regulation accuracy throughout the VID range from 0.75V
to 1.55V. Voltage regulation accuracy is slightly wider, ±5mV,
over the VID range from 0.7375V to 0.5V.
FIGURE 6. MODULATOR CIRCUITRY
The hysteresis window voltage is relative to the error amplifier
output such that load current transients result in increased
switching frequency, which gives the R 3 regulator a faster
response than conventional fixed frequency PWM controllers. In
uniplane configurations, transient load current is inherently
shared between active phases due to the use of a common
RIPPLE CAPACITOR VOLTAGE C R
WINDOW VOLTAGE V W
hysteretic window voltage. Individual average phase currents are
monitored and controlled to equally share current among the
active phases.
Modulator
The ISL6265C modulator features Intersil’s R 3 technology, a
hybrid of fixed frequency PWM control and variable frequency
hysteretic control (see Figure 6). Intersil’s R 3 technology can
simultaneously affect the PWM switching frequency and PWM
duty cycle in response to input voltage and output load
transients. The R 3 modulator synthesizes an AC signal V R , which
is an analog representation of the output inductor ripple current.
The duty-cycle of V R is the result of charge and discharge current
through a ripple capacitor C R . The current through C R is provided
by a transconductance amplifier g m that measures the VIN and
VO voltages. The positive slope of V R can be written as
determined by Equation 1:
ERROR AMPLIFIER VOLTAGE V COMP
PWM
FIGURE 7. MODULATOR WAVEFORMS DURING LOAD TRANSIENT
Initialization
Once sufficient bias is applied to the VCC pin, internal logic
checks the status of critical pins to determine the controller
operation profile prior to ENABLE. These pins include RTN1 which
determines single vs two-phase operation and OFS/VFIXEN for
enabling/disabling the SVI interface and core voltage droop.
V RPOS = ( g m ) ? ( V IN – V OUT )
The negative slope of V R can be written as determined by
Equation 2:
V RNEG = g m ? V OUT
Where g m is the gain of the transconductance amplifier.
14
(EQ. 1)
(EQ. 2)
Depending on the configuration set by these pins, the controller
then checks the state of the SVC and SVD pins to determine the
soft-start target output voltage level.
FN6976.2
January 11, 2013
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| ISL6265CIRTZ | 制造商:Intersil Corporation 功能描述:MULTI-OUTPUT CONTROLLER (SINGLE PHASE) WITH EMBEDDED GATE DR - Rail/Tube |
| ISL6265EVAL1Z | 制造商:Intersil Corporation 功能描述: |
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| ISL6265HRTZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6266AEVAL1Z | 功能描述:EVAL BOARD 1 FOR ISL6266A RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:* 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
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