参数资料
| 型号： | ISL6269AIRZ |
| 厂商： | Intersil |
| 文件页数： | 12/14页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-QFN |
| 标准包装： | 75 |
| 系列： | Robust Ripple Regulator™ (R³) |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 600kHz |
| 电源电压： | 5 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 包装： | 管件 |
ISL6269A
P CON_LS ≈ I LOAD ? r DS ( ON ) _LS ? ( 1 – D )
VOUT
LOW-SIDE
INDUCTOR
MOSFETS
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET
which has the drain-source voltage clamped by its body
diode during turn off, the high-side MOSFET turns off with
V IN - V OUT - V L across it. The preferred low-side MOSFET
emphasizes low r DS(ON) when fully saturated to minimize
conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as:
2
(EQ. 16)
For the high-side MOSFET, (HS), its conduction loss is
written as:
components, and the FSET components. The island should be
connected to the rest of the ground plane layer at one point.
VIAS TO GND
GROUND OUTPUT
PLANE CAPACITORS
SCHOTTKY
DIODE
PHASE
NODE
HIGH-SIDE
MOSFETS INPUT
VIN CAPACITORS
FIGURE 8. TYPICAL POWER COMPONENT PLACEMENT
Signal Ground and Power Ground
The bottom of the ISL6269A QFN package is the signal
P CON_HS = I LOAD
2
?
r DS ( ON ) _HS ? D
(EQ. 17)
ground (GND) terminal for analog and logic signals of the IC.
Connect the GND pad of the ISL6269A to the island of
ground plane under the top layer using several vias, for a
P SW_HS = ----------------------------------------------------------------- + -------------------------------------------------------------
Q g
C BOOT = ------------------------
Δ V BOOT
For the high-side MOSFET, its switching loss is written as:
V IN ? I VALLEY ? t ON ? f SW V IN ? I PEAK ? t OFF ? f SW
2 2
(EQ. 18)
Where:
- I VALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- I PEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- t ON is the time required to drive the device into
saturation
- t OFF is the time required to drive the device into cut-off
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as:
(EQ. 19)
Where:
- Q g is the total gate charge required to turn on the
high-side MOSFET
- Δ V BOOT , is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
As an example, suppose the high-side MOSFET has a total
gate charge Q g , of 25nC at V GS = 5V, and a Δ V BOOT of
200mV. The calculated bootstrap capacitance is 0.125μF; for
a comfortable margin select a capacitor that is double the
calculated capacitance, in this example 0.22μF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the compensation
12
robust thermal and electrical conduction path. Connect the
input capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground plane.
PGND (Pin 10)
This is the return path for the pull-down of the LG low-side
MOSFET gate driver. Ideally, PGND should be connected to
the source of the low-side MOSFET with a low-resistance,
low-inductance path .
VIN (Pin 1)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
VCC (Pin 2)
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
PVCC (Pin 12)
For best performance, place the decoupling capacitor very
close to the PVCC and PGND pins, preferably on the same
side of the PCB as the ISL6269A IC.
FCCM (Pin 3), EN (Pin 4), and PGOOD (Pin 16)
These are logic inputs that are referenced to the GND pin.
Treat as a typical logic signal.
COMP (Pin 5), FB (Pin 6), and VO (Pin 8)
For best results, use an isolated sense line from the output
load to the VO pin. The input impedance of the FB pin is
high, so place the voltage programming and loop
compensation components close to the VO, FB, and GND
pins keeping the high impedance trace short.
FSET (Pin 7)
This pin requires a quiet environment. The resistor R FSET
and capacitor C FSET should be placed directly adjacent to
this pin. Keep fast moving nodes away from this pin.
FN9253.2
May 30, 2007
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6269AIRZ-T | 功能描述:IC REG CTRLR BUCK PWM 16-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6269B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:High-Performance Notebook PWM Controller with Audio-Frequency Clamp |
| ISL6269BCRZ | 功能描述:IC REG CTRLR BUCK PWM 16-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6269BCRZ-T | 功能描述:IC REG CTRLR BUCK PWM 16-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6269BIRZ | 功能描述:IC REG CTRLR BUCK PWM 16-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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