参数资料
型号: ISL6273IRZ
厂商: Intersil
文件页数: 11/12页
文件大小: 0K
描述: IC BUCK SYNC ADJ 1.2A 10DFN
产品培训模块: Solutions for Industrial Control Applications
标准包装: 100
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5.5 V
输入电压: 2.7 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1.5MHz
电流 - 输出: 1.2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: *
封装/外壳: *
包装: *
供应商设备封装: *
ISL6273
Applications Information
Output Inductor and Capacitor Selection
To consider state steady and transient operation, ISL6273
typically uses a 1.8μH output inductor. Higher or lower
inductor value can be used to optimize the total converter
system performance. For example, for higher output voltage
3.3V application, in order to decrease the inductor current
ripple and output voltage ripple, the output inductor value
can be increased as shown in Table 1. The inductor ripple
current can be expressed as follows:
600
505
410
315
220
V O ? ? 1 – --------- ?
L ? f S
? V O ?
? V IN ?
Δ I = ---------------------------------------
125
30
0.8
1.27
1.73 2.2 2.67
OUTPUT VOLTAGE (V)
3.13
3.6
V O = 0.8 ? ? 1 + ------- ?
The inductor ’s saturation current rating needs be at least
larger than the peak current. The ISL6273 protects the peak
current 2.1A. The saturation current needs be over 2.1A for
maximum output current application.
ISL6273 uses internal compensation network and the output
capacitor value is dependant on the output voltage. The
ceramic capacitor is recommended to be X5R or X7R. The
recommended minimum output capacitor values are shown
in Table 1.
TABLE 1. OUTPUT CAPACITOR VALUE vs V OUT
FIGURE 20. THE MAXIMUM CAP vs THE OUTPUT VOLTAGE
Output Voltage Setting Resistor Selection
The resistors R2 and R3 shown in Figure 16 set the output
voltage for the adjustable version. The output voltage can be
calculated by:
? R 2 ?
? R 3 ?
where the 0.8V is the reference voltage. The voltage divider
0.8V
1.2V
1.6V
1.8V
2.5V
3.3V
3.6V
V OUT
10μF
10μF
10μF
10μF
10μF
6.8μF
4.7μF
C OUT
L
1.0μH~2.2μH
1.2μH~2.2μH
1.8μH~2.2μH
1.8μH~3.3μH
1.8μH~3.3μH
1.8μH~4.7μH
1.8μH~4.7μH
consists of R2 and R3 increases the quiescent current by
Vo/(R2+R3) so larger resistance is desirable. On the other
hand, the FB pin has leakage current that will cause error in
the output voltage setting. The leakage current has a typical
value of 0.1 μ A. To minimize the accuracy impact on the
output voltage, select the R3 no larger than 200k Ω .
Layout Recommendation
The layout is a very important converter design step to make
sure the designed converter works well. For ISL6273 buck
converter, the power loop is composed of the output inductor
L, the output capacitor C OUT , Phase pin and PGND pin. It is
In Table 1, the minimum output capacitor value is given for
different output voltage to make sure the whole converter
system stable. Due to the limitation on power dissipation
when the regulator disable and discharge output capacitor,
there is the maximum output capacitor value. The maximum
output capacitor value is variable with the output voltage.
The plot curve is shown in Figure 20.
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current flowing back to the
battery rail. A 10 μ F X5R or X7R ceramic capacitor is a good
starting point for the input capacitor selection.
11
necessary to make the power loop as small as possible. In
order to make the output voltage regulate well and avoid the
noise couple from the power loop specially for PFM mode
operation, SGND pin should be connected with PGND pin at
the terminals of the load.
The heat of the IC is mainly dissipated through the thermal
pad. Maximizing the copper area connected to the thermal
pad is preferable. In addition, a solid ground plane is helpful
for EMI performance.
FN9256.0
March 7, 2006
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