参数资料
型号: ISL62881DHRTZ-T
厂商: Intersil
文件页数: 16/37页
文件大小: 0K
描述: IC REG PWM SGL PHASE 32TQFN
标准包装: 6,000
应用: 控制器,Intel IMVP-6.5?
输入电压: 4.5 V ~ 25 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 带卷 (TR)
配用: ISL62881CCPUEVAL2Z-ND - EVAL BOARD ISL62881CCPU 28QFN
ISL62881C, ISL62881D
I droop = ------------------
R FSET ( k Ω ) = ( Period ( μ s ) – 0.29 ) × 2.65
the gain set by resistor R i . The current source is used for
load line implementation, current monitor and
overcurrent protection.
Figure 12 shows the load line implementation. The
ISL62881C drives a current source I droop out of the FB
pin, described by Equation 1.
2xV Cn (EQ. 1)
R i
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus sustaining the load
line accuracy with reduced cost.
I droop flows through resistor R droop and creates a
voltage drop as shown in Equation 2.
will increase during load insertion and will decrease
during load release to achieve fast response. On the
other hand, the switching frequency is relatively constant
at steady state. Variation is expected when the power
stage condition, such as input voltage, output voltage,
load, etc. changes. The variation is usually less than 15%
and doesn’t have any significant effect on output voltage
ripple magnitude. Equation 5 gives an estimate of the
frequency-setting resistor R fset value. 8k Ω R FSET gives
approximately 300kHz switching frequency. Lower
resistance gives higher switching frequency.
(EQ. 5)
Modes of Operation
TABLE 2. ISL62881C MODES OF OPERATION
V droop = R droop × I droop
(EQ. 2)
CONFIGURATION DPRSLPVR
OPERATIONAL
MODE
VOLTAGE
SLEW RATE
V droop is the droop voltage required to implement load
line. Changing R droop or scaling I droop can both change
the load line slope. Since I droop also sets the overcurrent
protection level, it is recommended to first scale I droop
based on OCP requirement, then select an appropriate
CPU VR Application
GPU VR Application
0
1
0
1
1-phase CCM
1-phase DE
1-phase CCM
1-phase DE
5mV/μs
5mV/μs
10mV/μs
R droop value to obtain the desired load line slope.
Differential Sensing
Figure 12 also shows the differential voltage sensing
scheme. VCC SENSE and VSS SENSE are the remote
voltage sensing signals from the processor die. A unity
gain differential amplifier senses the VSS SENSE voltage
and adds it to the DAC output. The error amplifier
regulates the inverting and the non-inverting input
voltages to be equal, therefore:
VCC SENSE + V droop = V DAC + VSS SENSE (EQ. 3)
Rewriting Equation 3 and substituting Equation 2 gives:
Table 2 shows the ISL62881C operational modes,
programmed by the logic status of the DPRSLPVR pin.
The ISL62881C enters 1-phase DE mode when there is
DPRSLPVR = 1.
When the ISL62881C is configured for GPU VR
application, DPRSLPVR logic status also controls the
output voltage slew rate. The slew rate is 5mV/μs for
DPRSLPVR = 0 and is 10mV/μs for DPRSLPVR = 1.
Dynamic Operation
When the ISL62881C is configured for CPU VR
application, it responds to VID changes by slewing to the
new voltage at 5mV/μs slew rate. As the output
VCC SENSE – VSS SENSE = V DAC – R droop × I droop
(EQ. 4)
approaches the VID command voltage, the dv/dt
moderates to prevent overshoot. Geyserville-III
Equation 4 is the exact equation required for load line
implementation.
The VCC SENSE and VSS SENSE signals come from the
processor die. The feedback will be open circuit in the
absence of the processor. As shown in Figure 12, it is
recommended to add a “catch” resistor to feed the VR
local output voltage back to the compensator, and add
another “catch” resistor to connect the VR local output
ground to the RTN pin. These resistors, typically
10 Ω ~100 Ω , will provide voltage feedback if the system is
powered up without a processor installed.
CCM Switching Frequency
The R FSET resistor between the COMP and the VW pins
sets the VW windows size, which therefore sets the
switching frequency. When the ISL62881C is in
continuous conduction mode (CCM), the switching
frequency is not absolutely constant due to the nature of
the R 3? modulator. As explained in “Multiphase R3?
Modulator” on page 12, the effective switching frequency
16
transitions commands one LSB VID step (12.5mV) every
2.5μs, controlling the effective dv/dt at 5mv/μs. The
ISL62881C is capable of 5mV/μs slew rate.
When the ISL62881C is configured for GPU VR
application, it responds to VID changes by slewing to the
new voltage at a slew rate set by the logic status on the
DPRSLPVR pin. The slew rate is 5mV/μs when
DPRSLPVR = 0 and is 10mV/μs when DPRSLPVR = 1.
When the ISL62881C is in DE mode, it will actively drive
the output voltage up when the VID changes to a higher
value. It’ll resume DE mode operation after reaching the
new voltage level. If the load is light enough to warrant
DCM, it will enter DCM after the inductor current has
crossed zero for four consecutive cycles. The ISL62881C
will remain in DE mode when the VID changes to a lower
value. The output voltage will decay to the new value and
the load will determine the slew rate.
During load insertion response, the Fast Clock function
increases the PWM pulse response speed. The
FN7596.0
March 8, 2010
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