参数资料
型号: ISL62881DHRTZ-T
厂商: Intersil
文件页数: 26/37页
文件大小: 0K
描述: IC REG PWM SGL PHASE 32TQFN
标准包装: 6,000
应用: 控制器,Intel IMVP-6.5?
输入电压: 4.5 V ~ 25 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 带卷 (TR)
配用: ISL62881CCPUEVAL2Z-ND - EVAL BOARD ISL62881CCPU 28QFN
ISL62881C, ISL62881D
TABLE 5. LAYOUT CONSIDERATIONS (Continued)
NAME
VSEN
RTN
VDD
IMON
ISUM-
ISUM+
LAYOUT CONSIDERATION
Place the VSEN/RTN filter (C12, C13) in close proximity of the controller for good decoupling.
A capacitor (C16) decouples it to GND. Place it in close proximity of the controller.
Place the filter capacitor (C21) close to the CPU.
Place the current sensing circuit in general proximity of the controller.
Place C82 very close to the controller.
Place NTC thermistors R 42 next to inductor (L1) so it senses the inductor temperature correctly.
The power stage sends a pair of VSUM+ and VSUM- signals to the controller. Run these two signal traces in parallel
fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads.
Route R 63 to the phase-node side pad of inductor L1. Route the other current sensing trace to the output side pad
of inductor L1.
If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to
the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of
the inductor. The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
VIAS
CURRENT-
SENSING TRACES
INDUCTOR
CURRENT-
SENSING TRACES
VIN
BOOT
UGATE
PHASE
A capacitor (C17) decouples it to GND. Place it in close proximity of the controller.
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE trace to the high-side MOSFET (Q2 and Q8) source pins
instead of general phase node copper.
VSSP Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
LGATE
or
LGATEa and
LGATEb
VCCP
VID0~6
VR_ON
crossing over or getting close. Recommend routing VSSP to the low-side MOSFET (Q3 and Q9) source pins instead
of general power ground plane for better performance.
A capacitor (C22) decouples it to GND. Place it in close proximity of the controller.
No special consideration.
No special consideration.
DPRSLPVR No special consideration.
Phase Node Minimize phase node copper area. Don’t let the phase node copper overlap with/getting close to other sensitive
traces. Cut the power ground plane to avoid overlapping with phase node copper.
Minimize the loop consisting of input capacitor, high-side MOSFETs and low-side MOSFETs (e.g.: C27, C33, Q2, Q8,
Q3 and Q9).
26
FN7596.0
March 8, 2010
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