参数资料
型号: ISL62883HRTZ-T
厂商: Intersil
文件页数: 23/37页
文件大小: 0K
描述: IC REG PWM 3PHASE BUCK 40TQFN
标准包装: 6,000
应用: 控制器,Intel IMVP-6.5?
输入电压: 5 V ~ 21 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
ISL62883, ISL62883B
Zout(s)=LL
i o
Q1
L
Vo
VID
VR
Load
Vo
Vin
GATE Q2
DRIVER
Cout
i o
LOAD LINE SLOPE
20 Ω
LOOP GAIN =
FIGURE 21. VOLTAGE REGULATOR EQUIVALENT CIRCUIT
Intersil provides a Microsoft Excel-based spreadsheet to help design
the compensator and the current sensing network, so the VR
achieves constant output impedance as a stable system. Please
contact Intersil Application support at www.intersil.com/design/ .
Figure 24 shows a screenshot of the spreadsheet.
A VR with active droop function is a dual-loop system consisting
of a voltage loop and a droop loop which is a current loop.
Mod. EA
Comp
CHANNEL B
CHANNEL A
CHANNEL A
NETWORK
ANALYZER
VID
EXCITATION
OUTPUT
ISOLATION
TRANSFORMER
CHANNEL B
However, neither loop alone is sufficient to describe the entire
system. The spreadsheet shows two loop gain transfer functions,
FIGURE 22. LOOP GAIN T1(s) MEASUREMENT SET-UP
T1(s) and T2(s), that describe the entire system. Figure 22
conceptually shows T1(s) measurement set-up and Figure 23
Q1
L
Vo
conceptually shows T2(s) measurement set-up. The VR senses
the inductor current, multiplies it by a gain of the load line slope,
then adds it on top of the sensed output voltage and feeds it to
Vin
GATE Q2
DRIVER
Cout
i o
the compensator. T(1) is measured after the summing node, and
T2(s) is measured in the voltage loop before the summing node.
The spreadsheet gives both T1(s) and T2(s) plots. However, only
LOAD LINE SLOPE
20
LOOP GAIN =
T2(s) can be actually measured on an ISL62883 regulator.
T1(s) is the total loop gain of the voltage loop and the droop loop.
It always has a higher crossover frequency than T2(s) and has
more meaning of system stability.
Mod. EA
Comp
CHANNEL B
CHANNEL A
Ω
VID
ISOLATION
TRANSFORMER
T2(s) is the voltage loop gain with closed droop loop. It has more
meaning of output voltage response.
Design the compensator to get stable T1(s) and T2(s) with
CHANNEL A
NETWORK
ANALYZER
EXCITATION
OUTPUT
CHANNEL B
sufficient phase margin, and output impedance equal or smaller
than the load line slope.
23
FIGURE 23. LOOP GAIN T2(s) MEASUREMENT SET-UP
FN6891.4
June 21, 2011
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