参数资料
型号: ISL62883IRTZ-T
厂商: Intersil
文件页数: 25/37页
文件大小: 0K
描述: IC REG PWM 3PHASE BUCK 40TQFN
标准包装: 6,000
应用: 控制器,Intel IMVP-6.5?
输入电压: 5 V ~ 21 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
ISL62883, ISL62883B
?
------------------------------ ?
I vid ( t ) = C vid × ------------ × ? 1 – e vid
dV fb R × C vid ?
? ?
? ?
dV fb C out × LL dV core
C vid × ------------ = ------------------------ × ------------------
R droop
Optional Slew Rate Compensation Circuit For
1-Tick VID Transition
Rdroop
Vcore
Rvid Cvid
OPTIONAL
FB Ivid
Idroop_vid
In the mean time, the R vid -C vid branch current I vid time domain
expression is shown in Equation 44:
– t
(EQ. 44)
dt
It is desired to let I vid (t) cancel I droop_vid (t). So there are :
(EQ. 45)
dt dt
and :
COMP
E/A
Σ VDAC DAC
VIDs
VID<0:6>
R vid × C vid = C out × LL
The result is expressed in Equation 47:
(EQ. 46)
RTN
VSSSENSE
R vid = R droop
(EQ. 47)
dV core
C out × LL
dt
C vid = ------------------------ × ------------------
R droop dV fb
dt
INTERNAL
TO IC
VID<0:6>
X1
VSS
and :
------------------
------------
(EQ. 48)
Vfb
Ivid
Vcore
Idroop_vid
FIGURE 25. OPTIONAL SLEW RATE COMPENSATION CIRCUIT
FOR1-TICK VID TRANSITION
During a large VID transition, the DAC steps through the VIDs at a
For example: given LL = 1.9m Ω , R droop = 2.37k Ω ,
C out = 1320μF, dV core /dt = 5mV/us and dV fb /dt = 15mV/μs,
Equation 47 gives R vid = 2.37k Ω and Equation 48 gives
C vid = 350pF.
It’s recommended to select the calculated R vid value and start
with the calculated C vid value and tweak it on the actual board to
get the best performance.
During normal transient response, the FB pin voltage is held
constant, therefore is virtual ground in small signal sense. The
R vid -C vid network is between the virtual ground and the real
ground, and hence has no effect on transient response.
Voltage Regulator Thermal Throttling
controlled slew rate of 2.5μs per tick (12.5mV), controlling
output voltage V core slew rate at 5mV/μs.
54uA
64uA
Figure 25 shows the waveforms of 1-tick VID transition. During
1-tick VID transition, the DAC output changes at approximately
15mV/μs slew rate, but the DAC cannot step through multiple
NTC
SW1
-
VR_TT#
VIDs to control the slew rate. Instead, the control loop response
speed determines V core slew rate. Ideally, V core will follow the FB
pin voltage slew rate. However, the controller senses the inductor
current increase during the up transition, as the I droop_vid
waveform shows, and will droop the output voltage V core
accordingly, making V core slew rate slow. Similar behavior occurs
during the down transition.
+
V NTC
-
R NTC
R s
1.24V
SW2
+
1.20V
INTERNAL TO
ISL62882
?
------------------------- ?
I droop ( t ) = ------------------------ × ------------------ × ? 1 – e out
C out × LL dV core C × LL ?
? ?
R droop
? ?
To control V core slew rate during 1-tick VID transition, one can add
the R vid -C vid branch, whose current I vid cancels I droop_vid .
When V core increases, the time domain expression of the
induced I droop change is expressed in Equation 43 :
– t
(EQ. 43)
dt
where C out is the total output capacitance.
25
FIGURE 26. CIRCUITRY ASSOCIATED WITH THE THERMAL
THROTTLING FEATURE OF THE ISL62882
FN6891.4
June 21, 2011
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