参数资料
型号: ISL62883IRTZ-T
厂商: Intersil
文件页数: 27/37页
文件大小: 0K
描述: IC REG PWM 3PHASE BUCK 40TQFN
标准包装: 6,000
应用: 控制器,Intel IMVP-6.5?
输入电压: 5 V ~ 21 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
ISL62883, ISL62883B
TABLE 5. LAYOUT CONSIDERATION (Continued)
TABLE 5. LAYOUT CONSIDERATION (Continued)
PIN
14
15
NAME
ISUM-
ISUM+
LAYOUT CONSIDERATION
Place the current sensing circuit in general
proximity of the controller.
Place C82 very close to the controller.
Place NTC thermistors R42 next to Phase-1
inductor (L1) so it senses the inductor temperature
correctly.
Each phase of the power stage sends a pair of
VSUM+ and VSUM- signals to the controller. Run
these two signals traces in parallel fashion with
decent width (>20mil).
IMPORTANT: Sense the inductor current by routing
the sensing circuit to the inductor pads.
Route R63 and R71 to the Phase-1 side pad of
PIN
25
26
27
28
29
NAME
VCCP
LGATE2
VSSP2
PHASE2
UGATE2
LAYOUT CONSIDERATION
A capacitor (C22) decouples it to GND. Place it in
close proximity of the controller.
Run these two traces in parallel fashion with
decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
Recommend routing VSSP2 to the Phase-2 low-
side MOSFET (Q5 and Q1) source pins instead of
general power ground plane for better
performance.
Run these two traces in parallel fashion with
decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
inductor L1. Route R88 to the output side pad of
inductor L1.
Route R65 and R72 to the Phase-2 side pad of
Recommend routing PHASE2 trace to the Phase-2
high-side MOSFET (Q4 and Q10) source pins
instead of general Phase-2 node copper.
inductor L2. Route R90 to the output side pad of
inductor L2.
Route R67 and R73 to the Phase-3 side pad of
inductor L3. Route R92 to the output side pad of
inductor L3.
30
31~37
BOOT2
VID0~6
Use decent wide trace (>30mil). Avoid any
sensitive analog signal trace from crossing over or
getting close.
No special consideration.
If possible. Route the traces on a different layer
from the inductor pad layer and use vias to
connect the traces to the center of the pads. If no
38
39
VR_ON No special consideration.
DPRSLPVR No special consideration.
via is allowed on the pad, consider routing the
traces into the pads from the inside of the
inductor. The following drawings show the two
preferred ways of routing current sensing traces.
40 CLK_EN# No special consideration.
Other Phase Node Minimize phase node copper area. Don’t let the
phase node copper overlap with/getting close to
other sensitive traces. Cut the power ground plane
Inductor
Inductor
Other
to avoid overlapping with phase node copper.
Minimize the loop consisting of input capacitor,
high-side MOSFETs and low-side MOSFETs (e.g.:
Vias
Current-Sensing
Traces
Current-Sensing
Traces
C27, C33, Q2, Q8, Q3 and Q9).
16
17
18
19
20
21
22
23
24
VDD
VIN
IMON
BOOT1
UGATE1
PHASE1
VSSP1
LGATE1
PWM3
A capacitor (C16) decouples it to GND. Place it in
close proximity of the controller.
A capacitor (C17) decouples it to GND. Place it in
close proximity of the controller.
Place the filter capacitor (C21) close to the CPU.
Use decent wide trace (>30mil). Avoid any
sensitive analog signal trace from crossing over or
getting close.
Run these two traces in parallel fashion with
decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
Recommend routing PHASE1 trace to the Phase-1
high-side MOSFET (Q2 and Q8) source pins instead
of general
Phase-1 node copper.
Run these two traces in parallel fashion with
decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
Recommend routing VSSP1 to the Phase-1 low-
side MOSFET (Q3 and Q9) source pins instead of
general power ground plane for better
performance.
No special consideration.
27
FN6891.4
June 21, 2011
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