参数资料
型号: ISL6308CRZ-T
厂商: Intersil
文件页数: 21/28页
文件大小: 0K
描述: IC CTRLR PWM 3PHASE BUCK 40-QFN
标准包装: 4,000
应用: 控制器,DDR
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 带卷 (TR)
ISL6308
1. Capture a transient event with the oscilloscope set to
about L/DCR/2 (sec/div). For example, with L = 1μH and
DCR = 1m Ω , set the oscilloscope to 500μs/div.
C 2 (Optional)
2. Record Δ V1 and Δ V2 as shown in Figure 18.
R 2
C 1
COMP
3. Select a new value, R COMP,2 , for the time constant
resistor based on the original value, R COMP,1 , using
Equation 27.
FB
R COMP , 2 = R COMP , 1 ? ----------
Δ V
Δ V 1
2
(EQ. 27)
R 1
ISL6308
4. Replace R COMP with the new value and check to see that
the error is corrected. Repeat the procedure if necessary.
After choosing a new value for R COMP , it will most likely be
necessary to adjust the value of R S to obtain the desired full
load droop voltage. Use Equation 26 to obtain the new value
for R S .
VDIFF
FIGURE 19. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6308 CIRCUIT
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
Δ V 1
Δ V 2
V OUT
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
The feedback resistor, R 1 , has already been chosen as
I TRAN
Δ I
FIGURE 18. TIME CONSTANT MISMATCH BEHAVIOR
Current Sensing)” on page 20 . Select a target bandwidth for
the compensated system, F 0 . The target bandwidth must be
large enough to assure adequate transient performance, but
smaller than one third of the per-channel switching frequency.
The values of the compensation components depend on the
relationships of F 0 to the L-C double pole frequency and the
ESR zero frequency. For each of the following three, there is a
separate set of equations for the compensation components.
Compensation
--------------------------- > F 0
R 2 = R 1 ? ------------------------------------------------------------
0.66 ? V
2 π ? V OSC ? R 1 ? f 0
--------------------------- ≤ F 0 < ---------------------------------
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
there are two distinct methods for achieving these goals.
Compensating the Load-Line Regulated Converter
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
Case 1:
Case 2:
1
2 π ? L ? C
2 π ? F 0 ? V OSC ? L ? C
IN
0.66 ? V IN
C 1 = -------------------------------------------------
1 1
2 π ? L ? C 2 π ? C ? ESR
V OSC ? ( 2 π ) 2 ? F 0 ? L ? C
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
2
0.66 ? V
R 2 = R 1 ? ----------------------------------------------------------------
IN
(EQ. 28)
compensation components, R 2 and C 1 .
21
0.66 ? V IN
2
C 1 = --------------------------------------------------------------------------------
( 2 π ) 2 ? F 0 ? V OSC ? R 1 ? L ? C
FN9208.4
September 30, 2008
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