参数资料
| 型号： | ISL6324AIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 15/40页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM DUAL 48QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页
ISL6324A
current through R ISEN which is proportional to the inductor
current. This current, I SEN , is continuously sensed and is
then used by the controller for load-line regulation, channel-
I ER toward zero. The same method for error signal
correction is applied to each active channel.
.
current balancing, and overcurrent detection and limiting.
Equation 9 shows that the proportion between the channel
current, I L , and the sensed current, I SEN , is driven by the
V COMP
+
-
MODULATOR
RAMP
+
-
PWM1
TO GATE
CONTROL
LOGIC
value of the effective sense resistance, R ISEN , and the DCR
of the inductor.
FILTER
f(s)
WAVEFORM
I SEN = I L ? ------------------
DCR
R ISEN
(EQ. 9)
I ER
-
I AVG
÷ N
Σ
I 4
I 3
The effective internal R ISEN resistance is important to the
current sensing process because it sets the gain of the load
+
I 2
line regulation loop when droop is enabled as well as the
gain of the channel-current balance loop and the overcurrent
trip level. The effective internal R ISEN resistance is user
programmable and is set through use of the RSET pin.
Placing a single resistor, R SET , from the RSET pin to the
VCC pin programs the effective internal R ISEN resistance
according to Equation 10.
I 1
NOTE: Channel 3 and 4 are optional.
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
VID Interface
The ISL6324A supports hybrid power control of AMD
R ISEN = ---------- ? R SET
3
400
(EQ. 10)
processors which operate from either a 6-bit parallel VID
interface (PVI) or a serial VID interface (SVI). The VID1/SEL
The North Bridge regulator samples the load current in the
same manner as the Core regulator does. The R SET resistor
will program all the effective internal R ISEN resistors to the
same value.
Channel-Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to
carry about the same amount of current at any load level. To
achieve this, the currents through each channel must be
sampled every switching cycle. The sampled currents, I n ,
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, I AVG , provides a measure of the total load
current demand on the converter during each switching
cycle. Channel-current balance is achieved by comparing
pin is used to command the ISL6324A into either the PVI
mode or the SVI mode. Whenever the EN pin is held LOW,
both the multi-phase Core and single-phase North Bridge
Regulators are disabled and the ISL6324A is continuously
sampling voltage on the VID1/SEL pin. When the EN pin is
toggled HIGH, the status of the VID1/SEL pin will latch the
ISL6324A into either PVI or SVI mode. This latching occurs
on the rising edge of the EN signal.If the VID1/SEL pin is
held LOW during the latch, the ISL6324A will be placed into
SVI mode. If the VID1/SEL pin is held HIGH during the latch,
the ISL6324A will be placed into PVI mode. For the
ISL6324A to properly enter into either mode, the level on the
VID1/SEL pin must be stable no less that 1μs prior to the EN
signal transitioning from low to high.
6-bit Parallel VID Interface (PVI)
With the ISL6324A in PVI mode, the single-phase North
Bridge regulator is disabled. Only the multi-phase controller
is active in PVI mode to support uniplane VDD only
processors. Table 1 shows the 6-bit parallel VID codes and
the corresponding reference voltage.
TABLE 1. 6-BIT PARALLEL VID CODES
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current
balance method is illustrated in Figure 6, with error
correction for Channel 1 represented. In the figure, the cycle
average current, I AVG , is compared with the Channel 1
sample, I 1 , to create an error signal I ER .
The filtered error signal modifies the pulse width
commanded by V COMP to correct any unbalance and force
VID5
0
0
0
0
0
0
0
0
VID4
0
0
0
0
0
0
0
0
VID3
0
0
0
0
0
0
0
0
VID2
0
0
0
0
1
1
1
1
VID1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
VREF
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
15
FN6880.2
May 14, 2010
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6324AIRZ-TR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ S - Tape and Reel 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324CRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324CRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324IRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324IRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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