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| 型号： | ISL6327ACRZ |
| 厂商： | Intersil |
| 文件页数： | 13/29页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 48-QFN |
| 标准包装： | 43 |
| PWM 型： | 控制器 |
| 输出数： | 6 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页
ISL6327A
offset errors in the OFS current source, remote-sense and
error amplifiers. Intersil specifies the guaranteed tolerance of
the ISL6327A to include the combined tolerances of each of
these elements.
The output of the error amplifier, V COMP , is compared to the
sawtooth waveforms to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
voltage. The internal and external circuitries, which control the
voltage regulation, are illustrated in Figure 5.
The ISL6327A incorporates an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground reference
point resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the
non-inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, V DIFF , is
connected to the inverting input of the error amplifier through an
external resistor.
A digital-to-analog converter (DAC) generates a reference
Load-Line Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of the output
voltage on the load current is often termed “droop” or “load
line” regulation. By adding a well controlled output
impedance, the output voltage can effectively be level shifted
in a direction which works to achieve the load-line regulation
required by these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from the fast changes of the load-current demand.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
TABLE 2. VR10 VID TABLE (WITH 6.25mV EXTENSION)
voltage based on the state of logic signals at pins VID7
VID4
VID3
VID2
VID1
VID0
VID5
VID6
VOLTAGE
through VID0. The DAC decodes the 8-bit logic signal (VID)
400mV
200mV
100mV
50mV
25mV
12.5mV 6.25mV
(V)
into one of the discrete voltages shown in Table 3. Each VID
input offers a 45μA pull-up to an internal 2.5V source for use
with open-drain outputs. The pull-up current diminishes to
zero above the logic threshold to protect voltage-sensitive
output devices. External pull-up resistors can augment the
pull-up current sources in case the leakage into the driving
device is greater than 45μA.
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0
1.6
1.59375
1.5875
1.58125
1.575
1.56875
EXTERNAL CIRCUIT
ISL6327A INTERNAL CIRCUIT
0
1
1
0
0
0
1
1.5625
R C
C C
COMP
0
1
1
0
0
0
0
1.55625
0
1
1
0
0
1
1
1.55
DAC
R REF
C REF
REF
+
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
1
0
1.54375
1.5375
1.53125
FB
-
V COMP
0
1
1
0
1
1
1
1.525
R FB
+
V DROOP
-
IDROOP
VDIFF
I AVG
ERROR AMPLIFIER
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1.51875
1.5125
0
1
1
1
0
0
0
1.50625
V OUT +
V OUT -
VSEN
RGND
+
-
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1.5
1.49375
1.4875
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 5. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
0
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
1
0
1
0
1.48125
1.475
1.46875
1.4625
1.45625
13
FN6833.0
February 17, 2009
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6327ACRZ-T | 功能描述:IC REG CTRLR BUCK PWM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6327AIRZ | 功能描述:IC REG CTRLR BUCK PWM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6327AIRZ-T | 功能描述:IC REG CTRLR BUCK PWM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6327CRZ | 功能描述:IC REG CTRLR BUCK PWM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6327CRZ-T | 功能描述:IC REG CTRLR BUCK PWM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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