参数资料
型号: ISL6327CRZ-T
厂商: Intersil
文件页数: 28/29页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 48-QFN
标准包装: 4,000
PWM 型: 控制器
输出数: 6
频率 - 最大: 1MHz
占空比: 25%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 48-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL6327
capacity while the two-phase converter would only require
10.9A RMS . The advantages become even more pronounced
when output current is increased and additional phases are
added to keep the component cost down relative to the
single phase approach.
Component Placement
Within the allotted implementation area, orient the switching
components first. The switching components are the most
critical because they carry large amounts of energy and tend
to generate high levels of noise. Switching component
0.3
I L(P-P) = 0
I L(P-P) = 0.25 I O
I L(P-P) = 0.5 I O
I L(P-P) = 0.75 I O
placement should take into account power dissipation. Align
the output inductors and MOSFETs such that spaces
between the components are minimized while creating the
PHASE plane. Place the Intersil MOSFET driver IC as close
0.2
0.1
as possible to the MOSFETs they control to reduce the
parasitic impedances due to trace length between critical
driver input and output signals. If possible, duplicate the
same placement of these components for each phase.
Next, place the input and output capacitors. Position one high-
frequency ceramic input capacitor next to each upper
MOSFET drain. Place the bulk input capacitors as close to the
upper MOSFET drains as dictated by the component size and
0
0
0.2
0.4
0.6
0.8
1.0
dimensions. Long distances between input capacitors and
DUTY CYCLE (V O/ V IN )
FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 4-PHASE CONVERTER
MOSFET drains result in too much trace inductance and a
reduction in capacitor performance. Locate the output
capacitors between the inductors and the load, while keeping
them in close proximity to the microprocessor socket.
0.6
The ISL6327 can be placed off to one side or centered
relative to the individual phase switching components.
Routing of sense lines and PWM signals will guide final
0.4
0.2
I L(P-P) = 0
I L(P-P) = 0.5 I O
I L(P-P) = 0.75 I O
0
0 0.2 0.4 0.6 0.8 1.0
DUTY CYCLE (V O/ V IN )
FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS
CURRENT vs DUTY CYCLE FOR SINGLE-PHASE
CONVERTER
Layout Considerations
The following layout strategies are intended to minimize the
impact of board parasitic impedances on converter
performance and to optimize the heat-dissipating capabilities
of the printed-circuit board. These sections highlight some
important practices which should not be overlooked during the
placement. Critical small signal components to place close
to the controller include the ISEN resistors, R T resistor,
feedback resistor, and compensation components.
Bypass capacitors for the ISL6327 and ISL66XX driver bias
supplies must be placed next to their respective pins. Trace
parasitic impedances will reduce their effectiveness.
Plane Allocation and Routing
Dedicate one solid layer, usually a middle layer, for a ground
plane. Make all critical component ground connections with
vias to this plane. Dedicate one additional layer for power
planes; breaking the plane up into smaller islands of
common voltage. Use the remaining layers for signal wiring.
Route phase planes of copper filled polygons on the top and
bottom once the switching component placement is set. Size
the trace width between the driver gate pins and the
MOSFET gates to carry 4A of current. When routing
components in the switching path, use short wide traces to
reduce the associated parasitic impedances.
layout process.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
28
FN9276.4
May 5, 2008
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