参数资料
| 型号： | ISL6333ACRZ |
| 厂商： | Intersil |
| 文件页数： | 33/40页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 3PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR11 |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6333, ISL6333A, ISL6333B, ISL6333C
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
I
L
the controller itself is the power dissipated in the upper drive
path resistance, P DR_UP , the lower drive path resistance,
P DR_UP , and in the boot strap diode, P BOOT . The rest of the
power will be dissipated by the external gate resistors (R G1
MOSFET
DRIVER
UGATE
LGATE
L
DCR
INDUCTOR
V L (s)
V OUT
C OUT
and R G2 ) and the internal gate resistors (R GI1 and R GI2 ) of
V C (s)
the MOSFETs. Figures 20 and 21 show the typical upper and
lower gate drives turn-on transition path. The total power
dissipation in the controller itself, P DR , can be roughly
I n
ISL6333 INTERNAL
CIRCUIT
R 1
C 1
estimated as calculated in Equation 32:
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q ? VCC )
SENSE
P BOOT = ---------------------
P Qg_Q1
3
+
-
V C (s)
R ISEN
ISEN-
ISEN+
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
? R HI1 R LO1 ? P Qg_Q1
3
(EQ. 32)
I SEN
RSET
VCC
P DR_LOW = ? ? ? ---------------------
? R HI2 + R EXT2 R LO2 + R EXT2 ?
? R HI2 R LO2 ? P Qg_Q2
-------------------------------------- + ----------------------------------------
2
R SET
FIGURE 22. DCR SENSING CONFIGURATION
R EXT1 = R G1 + -------------
R EXT2 = R G2 + -------------
R GI1
N Q1
R GI2
N Q2
Use Equation 34 to calculate the value of R SET . In
Equation 34, DCR is the DCR of the output inductor at room
temperature, I OCP is the desired overcurrent trip level, and
Inductor DCR Current Sensing Component
Selection
N is the number of phases. It is recommended that the
desired overcurrent trip level, I OCP , be chosen so that it’s
30% larger then the maximum load current expected.
R SET = ---------------------------- ? -------------- ? ----------
100 × 10
The controllers sense each individual channel’s inductor current
by detecting the voltage across the output inductor DCR of that
DCR I OCP 400
– 6 N 3
(EQ. 34)
page 21). As Figure 22 illustrates, an R-C network is required to
accurately sense the inductor DCR voltage and convert this
information into a current, which is proportional to the total
output current. The time constant of this R-C network must
match the time constant of the inductor L/DCR.
Follow the steps below to choose the component values for
this RC network.
1. Choose an arbitrary value for C 1 . The recommended
value is 0.1μF.
2. Plug the inductor L and DCR component values, and the
value for C 1 chosen in step 1, into Equation 33 to
calculate the value for R 1 .
Due to errors in the inductance or DCR it may be necessary
to adjust the value of R 1 to match the time constants
correctly. The effects of time constant mismatch can be seen
in the form of droop overshoot or undershoot during the
initial load transient spike, as shown in Figure 23. Follow the
steps below to ensure the R-C and inductor L/DCR time
constants are matched accurately.
1. Capture a transient event with the oscilloscope set to
about L/DCR/2 (sec/div). For example, with L = 1μH and
DCR = 1m Ω , set the oscilloscope to 500μs/div.
2. Record Δ V1 and Δ V2 as shown in Figure 23.
3. Select new values, R 1(NEW) , for the time constant
R 1 = -------------------------
L
DCR ? C 1
(EQ. 33)
resistor based on the original value, R 1(OLD) , using
Equation 35.
R 1 ( NEW ) = R 1 ( OLD ) ? ----------
Δ V
Once the R-C network components have been chosen, the
effective internal R ISEN resistance must then be set. The
R ISEN resistance sets the gain of the load line regulation loop
Δ V 1
2
(EQ. 35)
as well as the gain of the channel-current balance loop and the
overcurrent trip level. The effective internal R ISEN resistance is
set through a single resistor on the R SET pin, R SET .
33
4. Replace R 1 with the new value and check to see that the
error is corrected. Repeat the procedure if necessary.
FN6520.3
October 8, 2010
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6333ACRZ-T | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6333AEVAL1Z | 制造商:Intersil Corporation 功能描述: |
| ISL6333AIRZ | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:2,000 系列:- 应用:控制器，DSP 输入电压:4.5 V ~ 25 V 输出数:2 输出电压:最低可调至 1.2V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:30-TFSOP（0.173"，4.40mm 宽） 供应商设备封装:30-TSSOP 包装:带卷 (TR) |
| ISL6333AIRZ-T | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6333BCRZ | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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