参数资料
| 型号： | ISL6333CCRZ-T |
| 厂商： | Intersil |
| 文件页数： | 18/40页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 3PHASE BUCK 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR11 |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6333, ISL6333A, ISL6333B, ISL6333C
.
I L1 + I L2 + I L3 , 7A/DIV
I L3 , 7A/DIV
PWM3, 5V/DIV
I L2 , 7A/DIV
PWM2, 5V/DIV
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has
11.9A RMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
I L1 , 7A/DIV
INPUT-CAPACITOR CURRENT, 10A/DIV
PWM1, 5V/DIV
1μs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (I L1 , I L2 , and I L3 )
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle after the PWM pulse of the
previous phase. The peak-to-peak current for each phase is
about 7A, and the DC components of the inductor currents
combine to feed the load.
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine the equation representing an
CHANNEL 3
INPUT CURRENT
CHANNEL 2
INPUT CURRENT
CHANNEL 1
INPUT CURRENT
1μs/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND
INPUT-CAPACITOR RMS CURRENT FOR
3-PHASE CONVERTER
( V IN – V OUT ) ? V OUT
L ? f S ? V
individual channel peak-to-peak inductor current.
I PP = ----------------------------------------------------------
IN
(EQ. 1)
Active Pulse Positioning (APP) Modulated PWM
Operation
The controllers use a proprietary Active Pulse Positioning
In Equation 1, V IN and V OUT are the input and output
voltages respectively, L is the single-channel inductor value,
and f S is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
(APP) modulation scheme to control the internal PWM
signals that command each channel’s driver to turn their
upper and lower MOSFETs on and off. The time interval in
which a PWM signal can occur is generated by an internal
clock, whose cycle time is the inverse of the switching
frequency set by the resistor connected to the FS pin. The
advantage of Intersil’s proprietary Active Pulse Positioning
(APP) modulator is that the PWM signal has the ability to
turn on at any point during this PWM time interval, and turn
off immediately after the PWM signal transitions high. This is
important because it allows the controllers to quickly
respond to output voltage drops associated with current load
spikes, while avoiding the ring back affects associated with
other modulation schemes.
The PWM output state is driven by the position of the error
L ? f S ? V
( V IN – N ? V OUT ) ? V OUT
I C ( PP ) = --------------------------------------------------------------------
IN
(EQ. 2)
amplifier output signal, V COMP minus the current correction
signal relative to the proprietary modulator ramp waveform as
illustrated in Figure 4. At the beginning of each PWM time
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
18
interval, this modified V COMP signal is compared to the
internal modulator waveform. As long as the modified V COMP
voltage is lower then the modulator waveform voltage, the
PWM signal is commanded low. The internal MOSFET driver
detects the low state of the PWM signal and turns off the
FN6520.3
October 8, 2010
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相关代理商/技术参数 |
参数描述 |
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| ISL6333CIRZ | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6333CIRZ-T | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6333CRZ | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6333CRZ-T | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6333IRZ | 功能描述:IC CTRLR PWM 3PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
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