参数资料
型号: ISL6334CIRZ-T
厂商: Intersil
文件页数: 25/30页
文件大小: 0K
描述: IC CTRLR PWM SYNC BUCK 40-QFN
标准包装: 4,000
应用: 控制器,Intel VR11.1
输入电压: 3 V ~ 12 V
输出数: 1
输出电压: 0.5 V ~ 1.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 带卷 (TR)
ISL6334B, ISL6334C
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination
depends heavily upon the cost analysis, which in turn
depends on system constraints that differ from one design to
the next. Principally, the designer will be concerned with
whether components can be mounted on both sides of the
circuit board; whether through-hole components are
permitted; and the total board space available for power
supply circuitry. Generally speaking, the most economical
Upper MOSFET losses can be divided into separate
components involving the upper-MOSFET switching times;
the lower-MOSFET body-diode reverse-recovery charge, Q rr ;
and the upper MOSFET r DS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 25,
P UP , 1 ≈ V IN ? ------ + ---------- ? ? ---- 1 ? f S
solutions are those in which each phase handles between
15A and 25A. All surface-mount designs will tend toward the
lower end of this current range. If through-hole MOSFETs
and inductors can be used, higher per-phase currents are
possible. In cases where board space is the limiting
the required time for this commutation is t 1 and the
approximated associated power loss is P UP,1 .
I M I P-P ? t ?
? N 2 ? ? 2 ?
(EQ. 25)
constraint, current can be pushed as high as 40A per phase,
but these designs require heat sinks and forced air to cool
the MOSFETs, inductors and heat-dissipating surfaces.
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 26, the
approximate power loss is P UP,2 .
P UP , 2 ≈ V IN ? ------ – ---------- ? ? ---- 2 ? f S
MOSFETs
The choice of MOSFETs depends on the current each
? I M I P-P ? ? t ?
? N 2 ? ? 2 ?
(EQ. 26)
MOSFET will be required to conduct; the switching
frequency; the capability of the MOSFETs to dissipate heat;
and the availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
A third component involves the lower MOSFET’s reverse-
recovery charge, Q rr . Since the inductor current has fully
commutated to the upper MOSFET before the
lower-MOSFET’s body diode can draw all of Q rr , it is conducted
through the upper MOSFET across VIN. The power dissipated
as a result is P UP,3 and is approximated in Equation 27:
MOSFET is due to current conducted through the channel
P UP , 3 = V IN Q rr f S
(EQ. 27)
resistance (r DS(ON) ). In Equation 23, I M is the maximum
continuous output current; I P-P is the peak-to-peak inductor
current (see Equation 1); d is the duty cycle (V OUT /V IN ); and
L is the per-channel inductance.
Finally, the resistive part of the upper MOSFET’s is given in
Equation 28 as P UP,4 .
The total power dissipated by the upper MOSFET at full load
? I M ? 2 I L , P-P ( 1 – d )
? N ?
P LOW , 1 = r DS ( ON )
? ------ ? ( 1 – d ) + ----------------------------------
12
(EQ. 23)
can now be approximated as the summation of the results
from Equations 25, 26, and 27. Since the power equations
depend on MOSFET parameters, choosing the correct
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
MOSFETs can be an iterative process involving repetitive
solutions to the loss equations for different MOSFETs and
different switching frequencies, as shown in Equation 28.
I P-P2
? I M ?
P UP , 4 ≈ r DS ( ON ) ? ------ ? d + ---------- d
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I M , V D(ON) ; the switching
frequency, F sw ; and the length of dead times, t d1 and t d2 , at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
2
? N ? 12
Current Sensing Resistor
(EQ. 28)
I P-P ?
? I
P LOW , 2 = V D ( ON ) F sw ? ------ + I ---------- ? t
? d1 + ? ? ------ – ---------- ? ? d2
I M P-P M
? N
2 N 2
t
(EQ. 24)
The resistors connected to the ISEN+ pins determine the
gains in the load-line regulation loop and the channel-current
balance loop as well as setting the overcurrent trip point.
Thus the total maximum power dissipated in each lower
Select values for these resistors by using Equation 29:
R ISEN = --------------------------- --------------
105 × 10
MOSFET is approximated by the summation of P LOW,1 and
P LOW,2 .
R X I OCP
N
(EQ. 29)
Upper MOSFET Power Calculation
In addition to r DS(ON) losses, a large portion of the upper-
MOSFET losses are due to currents conducted across the
input voltage (V IN ) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent on
switching frequency, the power calculation is more complex.
25
where R ISEN is the sense resistor connected to the ISEN+
pin, N is the active channel number, R X is the resistance of
the current sense element, either the DCR of the inductor or
R SENSE depending on the sensing method, and I OCP is the
desired overcurrent trip point. Typically, I OCP can be chosen
FN6689.2
August 31, 2010
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