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参数资料
| 型号： | ISL6341IRZ |
| 厂商： | Intersil |
| 文件页数： | 11/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 10-TDFN |
| 标准包装： | 100 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 占空比： | 85% |
| 电源电压： | 4.5 V ~ 14.4 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 包装： | 管件 |
ISL6341, ISL6341A, ISL6341B, ISL6341C
PGOOD
The PGOOD function output monitors the output voltage
using the same VOS pin and resistor divider of the
undervoltage and overvoltage protection, but with separate
comparators for each. The rising OV trip point (10% above
but since the PGOOD UV and OV windows are tighter, the
PGOOD output should already be low by the time either
protection is tripped.
TABLE 2. PROTECTION SUMMARY
0.8V = 0.88V nominal on VOS) and the falling UV trip point
(10% below 0.8V = 0.72V nominal on VOS) will trip sooner
than the protection, in order to give an early warning to a
PROTECTION
OCP
ACTION TAKEN
VOUT latches off;
ENABLED
AFTER
POR or
RESET
BY
POR or
possible problem. The response time of the comparators
should be less than 1μs; the separate VOS input is not slowed
ISL6341
ISL6341B
LGATE and UGATE low.
COMP/EN COMP/EN
down by the compensation on the FB pin. It is NOT
OCP
Infinite retries; wait ~10ms,
POR or
Not
recommended to connect the VOS pin to the FB pin, in order
to share the resistor divider. If the VOS pin is accidentally
ISL6341A
ISL6341C
and try a new Soft-Start ramp. COMP/EN Applicable
ISL6341C has UVP disabled
disconnected, a small bias current on-chip will force an
overvoltage condition.
Figure 9 shows how the PGOOD output responds to a ramp
that trips in each direction (without reaching either protection
UVP
(-25%)
OVP
(+25%)
VOUT latches off;
LGATE and UGATE low.
ISL6341C has UVP disabled
VOUT latches off;
UGATE low;
after SS
ramp
POR
POR
POR
trip point at ±25%); PGOOD is valid (high) as long as V OUT
(and thus VOS) is within the ±10% window.
LGATE goes low and high to
keep VOUT within 50% and
125% of nominal.
VOS pin open will trigger OV.
110%
PGOOD
PGOOD goes low if VOS is
after SS
POR or
90%
V OUT (0.25V/DIV)
( UV; -10%)
PGOOD
( OV; +10%)
10% too low.
PGOOD goes low if VOS is
10% too high.
ramp
after SS
ramp
COMP/EN
POR or
COMP/EN
GND>
PGOOD
( OCP )
PGOOD goes low if OCP trips after SS
ramp
POR or
COMP/EN
or good
SS ramp
PGOOD (2V/DIV)
Switching Frequency
The switching frequency is a fixed 300kHz for the ISL6341,
ISL6341C and 600kHz for the ISL6341A, ISL6341B. It
GND>
FIGURE 9. PGOOD UNDERVOLTAGE AND OVERVOLTAGE
The PGOOD output is an open-drain pull-down NMOS
device; it can deliver 4.0mA of sink current at 0.3V when
power is NOT GOOD. A pull-up resistor to an external supply
voltage sets the high level voltage when power is GOOD. The
supply should be ≤ 6.0V, and is usually the one that powers
the logic monitoring the PGOOD output. If PGOOD function is
not used, the PGOOD pin can be left floating.
The PGOOD pin will be held low once V CC is above the rising
POR trip point, and during soft-start (but if the PGOOD supply
is up before or with V CC , it may be pulled high initially until the
logic has enough voltage to turn on the output). Once the
soft-start ramp is done (V OUT , VOS and FB should each be at
100% of their final value), the PGOOD pin will be allowed to
go high, if the output voltage is within the expected window.
There is no additional delay after soft-start is done.
Note that the overcurrent protection does directly affect the
PGOOD output, before the output voltage monitoring would
sense when V OUT drops 10%. The overvoltage and
undervoltage protection circuits don’t directly effect PGOOD,
11
cannot be adjusted externally, and the various soft-start
delays and ramps are fixed at the same times for either
frequency.
Output Voltage Selection
The output voltage can be programmed to any level between
the 0.8V internal reference, up to the V IN supply, with the
85% duty cycle restriction for the ISL6341, ISL6341C (75%
for the ISL6341A, ISL6341B). Additional duty cycle margin
due to the r DS(ON) drop across the upper FET at maximum
load needs to be factored in as well.
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage, and feed it
back to the inverting input of the error amp. See the “Typical
Application” schematic on page 3 for more detail; R S is the
upper resistor; R OFFSET (shortened to R O below) is the
lower one. The recommended value for R S is 1k Ω to 5k Ω
(±1% for accuracy) and then R OFFSET is chosen according
to Equation 2. Since R S is part of the compensation circuit
(see “Feedback Compensation” on page 13), it is often
easier to change R OFFSET to change the output voltage;
that way the compensation calculations do not need to be
FN6538.2
December 2, 2008
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相关代理商/技术参数 |
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|---|---|
| ISL6341IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 10-TDFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6353CRTZ | 功能描述:电流型 PWM 控制器 VR12 MEMORY CNTRLR 3 PHS 2 INT 5V DRVRS RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6353CRTZ-T | 功能描述:电流型 PWM 控制器 VR12 MEMORY CNTRLR 3 PHS 2 INT 5V DRVRS RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6353CRTZ-TS2568 | 制造商:Intersil Corporation 功能描述:INTEL, ISL6353CRTZ-T W/BARCODE LABELS, 12 MONTH D/C RESTRICT - Tape and Reel |
| ISL6353CRZ | 制造商:Intersil 功能描述:Multiphase PWM Regulator for VR12 DDR Memory Systems |
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