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参数资料
| 型号： | ISL6405I2C-KIT-EVAL |
| 厂商： | Intersil |
| 文件页数： | 9/13页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD I2C ISL6405 |
| 标准包装： | 1 |
| 主要目的： | 特殊用途 DC/DC，LNB |
| 输出及类型： | 2，非隔离 |
| 输入电压： | 8 ~ 14 V |
| 稳压器拓扑结构： | 降压 |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL6405 |
ISL6405
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 3).
The peripheral that acknowledges has to pull down (LOW)
the SDA line during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6405 will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data.
This approach, though, is less protected from error and
decreases the noise immunity.
ISL6405 Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
? A start condition (S)
? A chip address byte (MSB on left; the LSB bit determines
read (1) or write (0) transmission) (the assigned I 2 C slave
address for the ISL6405 is 0001 00XX)
? A sequence of data (1 byte + Acknowledge)
? A stop condition (P)
TABLE 2. INTERFACE PROTOCOL
SCL
1
2
8
9
S 0
0
0
1
0
0
0 R/W ACK
Data (8 bits)
ACK P
SDA
System Register Format
START
MSB
ACKNOWLEDGE
FROM SLAVE
? R, W = Read and Write bit
? R = Read-only bit
All bits reset to 0 at Power-On
FIGURE 3. ACKNOWLEDGE ON THE I 2 C BUS
TABLE 3. SYSTEM REGISTER 1 (SR1)
R, W
SR1
R, W
DCL
R, W
ISEL1
R, W
ENT1
R, W
LLC1
R, W
VSEL1
R, W
EN1
R
OLF1
TABLE 4. SYSTEM REGISTER 2 (SR2)
R, W
SR2
R, W
ISEL2
R, W
ENT2
R, W
LLC2
R, W
VSEL2
R, W
EN2
R
OTF
R
OLF2
9
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相关代理商/技术参数 |
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| ISL6406CB | 制造商:Rochester Electronics LLC 功能描述:HI EFFICIENCY, LO VOLTAGE, SINGLE PWM W/ADJ. OUTPUT - Bulk |
| ISL6406CB-T | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| ISL6406CR | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intersil Corporation 功能描述: |
| ISL6406CRZ | 制造商:Intersil Corporation 功能描述: |
| ISL6406CV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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