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参数资料
| 型号： | ISL6421AEVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 1 FOR ISL6421A |
| 标准包装： | 1 |
| 系列： | * |
ISL6421A
Received Data ( I 2 C Bus Read Mode)
The ISL6421A can provide to the master a copy of the
System Register information via the I 2 C bus in read mode.
The read mode is Master activated by sending the chip
address with R/W bit set to 1. At the following Master
generated clock bits, the ISL6421A issues a byte on the
SDA data bus line (MSB transmitted first).
At the ninth clock bit the MCU master can:
? Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6421A.
? Not acknowledge, stopping the read mode
communication.
While the whole register is read back by the microprocessor,
only the two read-only bits, OLF and OTF, convey diagnostic
information about the ISL6421A.
TABLE 6. READING SYSTEM REGISTERS
Power-On I 2 C Interface Reset
The I 2 C interface built into the ISL6421A is automatically
reset at power-on. The I 2 C interface block will receive a
Power OK logic signal from the UVLO circuit. This signal will
go HIGH when chip power is OK. As long as this signal is
LOW, the interface will not respond to any I 2 C commands
and the system register SR is initialized to all zeros, thus
keeping the power blocks disabled.
Once Vcc rises above the UVLO level, the POWER OK
signal given to the I 2 C interface block will be HIGH, the I 2 C
interface becomes operative and the SR can be configured
by the main microprocessor. About 400mV of hysteresis is
provided in the UVLO threshold to avoid false triggering of
the Power-On reset circuit.
(I 2 C comes up with EN = 0, EN goes HIGH at the same time
as (or later than) all other I 2 C data for the PWM becomes
valid).
DCL ISEL ENT LLC VSEL EN OTF OLF
These bits are read as they were 0
after the last write operation.
1
FUNCTION
Tj ≤ 130°C, Normal
operation
Tj > 150°C, Power
blocks disabled
ADDRESS Pin
Connecting this pin to GND forces the chip I 2 C interface
address to 0001000; applying a voltage >2.7V forces the
address to 0001001, as shown below.
TABLE 7. ADDRESS PIN CHARACTERISTICS
0
Iout < Imax, Normal
operation
Vaddr
Vaddr-1
MIN
0V
TYP
-
MAX
2.0V
1
Iout > Imax, Overload
“0001000”
protection triggered
Vaddr-2
2.7V
-
5.0V
“0001001”
I 2 C Electrical Specifications
TABLE 8. I 2 C SPECIFICATIONS
PARAMETER
TEST CONDITION
MINIMUM
TYPICAL
MAXIMUM
Input Logic High, VIH
Input Logic Low, VIL
Input Logic Current, IIL
SDA, SCL
SDA, SCL
SDA, SCL; 0.4V < Vin < 4.5V
0.7 x V DD
0.3 x V DD
10 μ A
SCL Clock Frequency
0
100kHz
400kHz
NOTE: V DD = 5.0V/3.3V.
9
FN9167.3
March 9, 2006
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| ISL6421ERZ-T | 功能描述:电流型 PWM 控制器 SINGLE LNBP SUPPLY CONTROL VG 32LD MLFP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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