参数资料
型号: ISL6422BERZ-T
厂商: Intersil
文件页数: 16/18页
文件大小: 0K
描述: IC VREG DUAL LNB W/I2C 40-QFN
标准包装: 4,000
应用: 转换器,卫星信号接收机顶盒设计
输入电压: 8 V ~ 14 V
输出数: 2
输出电压: 13.3 V ~ 18.3 V,14.3 V ~ 19.3 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 带卷 (TR)
ISL6422B
keeping the power blocks disabled. Once the V CC rises
above UVLO, the POWER OK signal given to the I 2 C
interface block will be HIGH, the I 2 C interface becomes
TABLE 19. ADDRESS PIN CHARACTERISTICS
V ADDR ADDR1 ADDR0
operative and the SRs can be configured by the main
microprocessor. About 400mV of hysteresis is provided in the
UVLO threshold to avoid false triggering of the Power-On
reset circuit. (I 2 C comes up with EN = 0; EN goes HIGH at the
same time as (or later than) all other I 2 C data for that PWM
becomes valid).
ADDRESS Pin
Connecting this pin to GND the chip I 2 C interface address is
V ADDR -1
“0001000”
V ADDR -2
“0001001”
V ADDR -3
“0001010”
V ADDR -4
“0001011”
0
0
1
1
0
1
0
1
0001000, but, it is possible to choose between four different
addresses simply by setting this pin at one of the four fixed
voltage levels, as shown in Table 19.
I 2 C Electrical Characteristics
TABLE 20. I 2 C SPECIFICATIONS
PARAMETER
TEST CONDITION
MIN
TYP
MAX
Input Logic High, VIH
Input Logic Low, VIL
Input Logic Current, IIL
SDA, SCL
SDA, SCL
SDA, SCL;
0.4V < V DD < 3.3V
2.0V
0.8V
10 μ A
Input Hysterisis
SCL Clock Frequency
SDA, SCL
165mV
0
200mV
100kHz
235mV
400kHz
I 2 C Bit Description
TABLE 21.
BIT NAME
EN1, EN2
VTOP1, VTOP2
VBOT1, VBOT2
ENT1, ENT2
MSEL1, MSEL2
TFR1, TFR2
DCL1, DCL2
VSPEN1, VSPEN2
ISELH1, SELH2 and ISELL1,
ISELL2, ISEL1R, ISEL2R
OTF
CABF1, CABF2
OUVF1, OUVF2
OLF1, OLF2
BCF1, BCF2
TTH1, TTH2
16
DESCRIPTION
ENable output for Channels 1 and 2
Voltage TOP Select ie 18V/19V for Channels 1 and 2
Voltage BOTtom Select, i.e. 13V/14V for Channels 1 and 2
ENable Tone for Channels 1 and 2
Modulation SELect for Channels 1 and 2
Tone Frequency and Rise time select for Channels 1 and 2
Dynamic Current Limit select for Channels 1 and 2
Voltage Select Pin ENable for Channels 1 and 2
Current limit “I” SELect High and Low bits for Channels 1 and 2
Over-Temperature Fault bit
CABle Fault or open status bit for Channels 1 and 2
Over and Undervoltage Fault status bit for Channels 1 and 2
Over Load Fault status bit for Channels 1 and 2
Backward Current Fault bit for Channels 1 and 2
Tone THreshold is the OR of the signal pin TXT1, TXT2
FN6486.1
August 10, 2007
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