参数资料
型号: ISL6425EVAL2
厂商: Intersil
文件页数: 11/12页
文件大小: 0K
描述: EVAL BOARD 2 FOR ISL6425
标准包装: 1
系列: *
ISL6425
Once Vcc rises above the UVLO level, the POWER OK
signal given to the I 2 C interface block will be HIGH, the I 2 C
interface becomes operative and the SR can be configured
I 2 C Electrical Characteristics
TABLE 8. I 2 C SPECIFICATIONS
by the main microprocessor. About 400mV of hysteresis is
provided in the UVLO threshold to avoid false triggering of
PARAMETER
TEST
CONDITION
MIN
TYP
MAX
the Power-On reset circuit.
(I 2 C comes up with EN = 0, EN goes HIGH at the same time
as (or later than) all other I 2 C data for the PWM becomes
valid).
Input Logic High, SDA, SCL
VIH
Input Logic Low, SDA, SCL
VIL
0.7 x V DD
0.3 x V DD
ADDRESS Pin
Connecting this pin to GND forces the chip I 2 C interface
address to 0001000; applying a voltage >2.7V forces the
address to 0001001, as shown below.
Input Logic
Current, IIL
SCL Clock
Frequency
SDA, SCL;
0.4V < Vin < 4.5V
0
100kHz
10 μ A
400kHz
TABLE 7. ADDRESS PIN CHARACTERISTICS
VADDR
Vaddr-1
MIN
0V
TYP
-
MAX
2.0V
“0001000”
Vaddr-2
2.7V
-
5.0V
“0001001”
11
FN9176.1
February 8, 2005
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