参数资料
型号: ISL6455AIRZ-T5K
厂商: Intersil
文件页数: 11/12页
文件大小: 0K
描述: IC REG PWM 0.6A DUAL LDO 24-QFN
标准包装: 5,000
应用: 转换器,FPGAs
输入电压: 4.2 V ~ 5.5 V
输出数: 3
输出电压: 0.8 V ~ 3.3 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-QFN(4x4)
包装: 带卷 (TR)
ISL6455, ISL6455A
I RMS = I O ( max ) × -------- × ? 1 – -------- ?
the inductor. The DC resistance of the inductor will influence
directly the efficiency of the converter. Therefore, an inductor
with lowest DC resistance should be selected for highest
efficiency.
In order to avoid saturation of the inductor, the inductor
should be rated at least for the maximum output current plus
the inductor ripple current.
TABLE 1. RECOMMENDED INDUCTORS
The input capacitor should have a minimum value of 10μF
and can be increased without any limit for better input
voltage filtering. The input capacitor should be rated for the
maximum input ripple current calculated as:
V O ? V O ?
V I ? V I ?
The worst case RMS ripple current occurs at D = 0.5.
OUTPUT
CURRENT
600mA
600mA
INDUCTOR
VALUE
8.2 μ H
12 μ H
VENDOR PART #
Coilcraft
MSS6122-822MX
Coilcraft
MSS6122-123MX
COMMENTS
ISL6455
ISL6455A
Ceramic capacitors show good performance because of
their low ESR value, and because they are less sensitive to
voltage transients, compared to tantalum capacitors.
Place the input capacitor as close as possible to the input pin
of the IC for best performance.
Output Voltage Setting
VOUT = ----------- ( Re + Rf )
VOUT1 = --------------- ( Ra + Rb )
OUTPUT CAPACITOR SELECTION
For the best performance, a low ESR output capacitor is
needed. If an output capacitor is selected with an ESR value
≤ 120m ? , its RMS ripple current rating will always meet the
application requirements. The RMS ripple current is
calculated as:
The equations for the Output voltages are given below:
0.45
Rf
1.184
Rb
V O
= V O × ----------------- × -----------------
VOUT2 = --------------- ( Rc + Rd )
I RMS ( C )
O
1 – --------
V I 1
L × f 2 × 3
1.184
Rd
? 1 – ------- ?
V I
? V O = V O × ? ----------------- ? × ? -------------------------- + ESR ?
? L × f ? ? 8 × C × f ?
? ?
The overall output ripple voltage is the sum of the voltage
spike caused by the output capacitor ESR plus the voltage
ripple caused by charge and discharging the output
capacitor:
? ?
1
O
? ?
Where the highest output voltage ripple occurs at the highest
input voltage.
TABLE 2. RECOMMENDED CAPACITORS
CAPACITOR
The output resistors should be selected so that the minimum
output load is about 200 μ A.
Layout Considerations
As for all switching power supplies, the layout is an important
step in the design of ISL6455, ISL6455A based power
supply due to the high switching frequency and low noise
LDO implementations.
Allocate two board levels as ground planes, with many vias
between them to create a low impedance, high-frequency
plane. Tie all the device ground pins through multiple vias
each to this ground plane, as close to the device as possible.
Also tie the exposed pad on the bottom of the device to this
ground plane.
VALUE
10 μ F
ESR/m ?
<50
VENDOR PART #
TDK
C2012X5R0J106M
COMMENTS
Ceramic
Use wide and short traces for the high current paths. The
input capacitor should be placed as close as possible to the
IC pins as well as the inductor and output capacitor. Use a
common ground node to minimize the effects of ground
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a
pulsating input current, a low ESR input capacitor is required
for best input voltage filtering and minimizing the
interference with other circuits caused by high input voltage
spikes.
11
noise.
FN9196.0
December 21, 2005
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