参数资料
型号: ISL6521CBZ-TS2698
厂商: Intersil
文件页数: 7/13页
文件大小: 639K
描述: IC REG QD BCK/LINEAR 16-SOIC
标准包装: 2,500
拓扑: 降压(降压)同步(1),线性(LDO)(3)
功能: 任何功能
输出数: 4
频率 - 开关: 300kHz
电压/电流 - 输出 1: 控制器
电压/电流 - 输出 2: 可调式,120mA
电压/电流 - 输出 3: 可调式,120mA
带 LED 驱动器:
带监控器:
带序列发生器:
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: *
包装: 带卷 (TR)
7
The OC trip point varies with MOSFETs r
DS(ON)
 
temperature variations. To avoid overcurrent tripping in the
normal operating load range, determine the R
OCSET
 
resistor from the equation above with:
1. The maximum r
DS(ON)
 at the highest junction temperature.
2. The minimum I
OCSET
 from the specification table.
3. Determine I
PEAK
 for I
PEAK
 > I
OUT(MAX)
 + (I) / 2, where
I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled Output Inductor Selection.
Output Voltage Selection
The output voltage of the PWM converter can be resistor-
programmed to any level between V
IN
 and 0.8V . However,
since the value of R
S1
 is affecting the values of the rest of
the compensation components, it is advisable its value is
kept between 2k& and 5k&.
Output voltage selection on the linear regulators is set by
means of external resistor dividers as shown in Figure 4.
The two resistors used to set the voltage on each of the
three linear regulators have to meet the following criteria:
their value while in a parallel connection has to be less than
5k&, or otherwise said, the following relationship has to be
met:
To ensure the parallel combination of the feedback resistors
equals a certain chosen value, R
FB
, use the following
equations:
, where
V
OUT
 - the desired output voltage,
V
FB
 - feedback (reference) voltage, 0.8V.
Application Guidelines
Soft-Start Interval
The soft-start function controls the output voltages rate of rise
to limit the current surge at start-up. The soft-start function is
integrated on the chip and the soft-start interval is fixed.
PWM Controller Feedback Compensation
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration
for a PWM voltage-mode controller. Apply the methods and
considerations only to the PWM controller.
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the reference voltage level, 0.8V. The
error amplifier (Error Amp) output (V
E/A
) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
IN
 at the
PHASE node. The PWM wave is smoothed by the output
filter (L
O
 and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
 . This function is dominated by a DC
Gain, given by V
IN
/V
OSC
 , and shaped by the output filter,
with a double pole break frequency at F
LC
 and a zero at
F
ESR
 .
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6521) and the impedance networks Z
IN
 
UGATE
OCSET
PHASE
OCC
+
-
GATE
CONTROL
VCC
OC
40?/SPAN>A
V
DS(ON)
i
D
V
SET
R
OCSET
V
IN
 = +5V
OVERCURRENT TRIP:
I
OCSET
+
+
FIGURE 3. OVERCURRENT DETECTION
PWM
DRIVE
i
D
r
DS ON
(  )
?/DIV>
I
OCSET
R
OCSET
?/DIV>
>
V
DS
V
SET
>
V
PHASE
V
IN
V
DS

=
V
OCSET
V
IN
V
SET

=
DRIVE3
FB3
FB4
C
OUT4
C
OUT3
Q3
ISL6521
V
OUT3
V
OUT4
+5V
IN
DRIVE4
R
S3
R
P3
R
S4
R
P4
V
OUT
0.8  1
R
S
R
P
--------
+
?nbsp   ?/DIV>
?nbsp   ?/DIV>
?nbsp   ?/DIV>
?/DIV>
=
FIGURE 4. ADJUSTING THE OUTPUT VOLTAGE OF ANY OF
THE FOUR REGULATORS (OUTPUTS 3 AND 4
PICTURED)
+
+
R
S
R
P
?/DIV>
R
S
R
P
+
---------------------- 5k&
<
R
S
V
OUT
V
FB
----------------
R
FB
?/DIV>
=
R
P
R
S
V
FB
?/DIV>
V
OUT
V
FB

---------------------------------
=
F
LC
1
2?nbsp L
O
C
O
?/DIV>
?/DIV>
----------------------------------------
=
F
ESR
1
2?ESR C
O
?/DIV>
?/DIV>
-----------------------------------------
=
ISL6521
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