参数资料
| 型号： | ISL6548CRZA |
| 厂商： | Intersil |
| 文件页数： | 12/15页 |
| 文件大小： | 0K |
| 描述： | IC REG/CTRLR ACPI DUAL DDR 28QFN |
| 标准包装： | 50 |
| 应用： | 存储器，DDR/DDR2 稳压器 |
| 电流 - 电源： | 7mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（6x6） |
| 包装： | 管件 |
ISL6548
F Z1 = ------------------------------------
F P1 = ---------------------------------------------------------
2 π x R 2 x ? ?
F Z2 = -------------------------------------------------------
F P2 = ------------------------------------
? V OSC
OSC
PWM
COMPARATOR
-
+
DRIVER
DRIVER
V IN
L O
PHASE
C O
ESR
V DDQ
Compensation Break Frequency Equations
1 1
2 π x R 2 x C 1 ? C 1 x C 2 ?
----------------------
? C 1 + C 2 ?
1 1
2 π x ( R 1 + R 3 ) x C 3 2 π x R 3 x C 3
V E/A
Z FB
(PARASITIC)
Figure 4 shows an asymptotic plot of the DC/DC converter ’s
-
+
ERROR
AMP
Z IN
REFERENCE
gain vs. frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 4. Using the above guidelines should
DETAILED COMPENSATION COMPONENTS
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
C 2
C 1
R 2
Z FB
C 3
Z IN
R 3
V DDQ
gain. Check the compensation gain at F P2 with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 4 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
COMP
-
FB
R 1
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
V DDQ = 0.8 × ? 1 + ------ 1 - ?
+
ISL6548
REFERENCE
? R ?
? R 4 ?
R 4
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
FIGURE 3. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
100
F Z1 F Z2
F P1
F P2
80
Modulator Break Frequency Equations
60
OPEN LOOP
ERROR AMP GAIN
F LC = -------------------------------------------
LO x CO
F ESR = --------------------------------------------
2 π x
1
1
2 π x ESR x C O
40
20
20LOG
(R 2 /R 1 )
20LOG
The compensation network consists of the error amplifier
0
(V IN / ? V OSC )
F ESR
(internal to the ISL6548) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f 0dB and
180 degrees. The equations below relate the compensation
-20
-40
-60
10
MODULATOR
GAIN
100
1K
F LC
10K 100K
FREQUENCY (Hz)
1M
COMPENSATION
GAIN
CLOSED LOOP
GAIN
10M
network’s poles, zeros and gain to the components (R 1 , R 2 ,
R 3 , C 1 , C 2 , and C 3 ) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R 2 /R 1 ) for desired converter bandwidth.
2. Place 1 ST Zero Below Filter’s Double Pole (~75% F LC ).
3. Place 2 ND Zero at Filter ’s Double Pole.
4. Place 1 ST Pole at the ESR Zero.
5. Place 2 ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier ’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
12
FIGURE 4. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Output Voltage Selection
The output voltage of the all the external voltage regulators
converter can be programmed to any level between their
individual input voltage and the internal reference, 0.8V. An
external resistor divider is used to scale the output voltage
relative to the reference voltage and feed it back to the
inverting input of the error amplifier, refer to the Typical
Application on page 3.
FN9188.2
January 3, 2006
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6551IR-T | IC REG CTRLR FLYBACK PWM 28-QFN |
| ISL6552CR-T | IC REG CTRLR BUCK PWM 20-QFN |
| ISL6553CB-T | IC REG CTRLR BUCK PWM 16-SOIC |
| ISL6554CB-T | IC PWM CORE VOLTAGE REG 20-SOIC |
| ISL6556ACR-T | IC CTRLR MULTIPHASE VRM10 32-QFN |
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