参数资料
型号: ISL6553CB-T
厂商: Intersil
文件页数: 15/15页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 16-SOIC
标准包装: 2,500
PWM 型: 控制器
输出数: 1
频率 - 最大: 1.5MHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
ISL6553
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INCHES
MILLIMETERS
INDEX
AREA
E
H
0.25(0.010) M
B M
SYMBOL
A
MIN
0.053
MAX
0.069
MIN
1.35
MAX
1.75
NOTES
-
-B-
A1
0.004
0.010
0.10
0.25
-
1
2
3
L
B
C
0.014
0.007
0.019
0.010
0.35
0.19
0.49
0.25
9
-
SEATING PLANE
D
0.386
0.394
9.80
10.00
3
-A-
D
A
h x 45 o
E
e
0.150 0.157
0.050 BSC
3.80 4.00
1.27 BSC
4
-
e
-C-
A1
μ α
C
H
h
L
0.228
0.010
0.016
0.244
0.020
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
5
6
B
0.10(0.004)
N
16
16
7
0.25(0.010) M
C A M
B S
α
0 o
8 o
0 o
8 o
-
Rev. 1 02/02
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
15
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