参数资料
| 型号： | ISL6553CB-T |
| 厂商： | Intersil |
| 文件页数： | 9/15页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 1.5MHz |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
ISL6553
Under-Voltage
The VSEN pin also detects when the CORE voltage falls
more than 10% below the VID programmed level. This
causes PGOOD to go low, but has no other effect on
operation and is not latched. There is also hysteresis in this
detection point.
Table 1 shows the nominal DAC voltage as a function of the
VID codes. The power supply system is ± 1% accurate over
the operating temperature and voltage range.
TABLE 1. VOLTAGE IDENTIFICATION CODES
VOLTAGE IDENTIFICATION CODE AT
Over-Current
PROCESSOR PINS
VCC (CORE)
In the event of an over-current condition, the over-current
protection circuit reduces the RMS current delivered to 41%
of the current limit. When an over-current condition is
detected, the controller forces all PWM outputs into a three
state mode. This condition results in the gate driver
removing drive to the output stages. The ISL6553 goes into
a wait delay timing cycle that is equal to the Soft-Start ramp
time. PGOOD also goes “low” during this time due to VSEN
going below its threshold voltage. To lower the average
output dissipation, the Soft-Start initial wait time is increased
from 32 to 2048 cycles, then the Soft-Start ramp is initiated.
At a PWM frequency of 200kHz, for instance, an over-current
detection would cause a dead time of 10.24ms, then a ramp
of 10.08ms.
At the end of the delay, PWM outputs are restarted and the
Soft-Start ramp is initiated. If a short is present at that time,
the cycle is repeated. This is the hiccup mode.
Figure 6 shows the supply shorted under operation and the
hiccup operating mode described above. Note that due to
the high short circuit current, over-current is detected before
completion of the start-up sequence so the delay is not quite
as long as the normal Soft-Start cycle.
SHORT APPLIED HERE
PGOOD
SHORT
VID25mV
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VID3
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
VID2
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
VID1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
(VDC)
1.05
1.075
1.10
1.125
1.15
1.175
1.20
1.225
1.25
1.275
1.30
1.325
1.35
1.375
1.40
1.425
1.45
1.475
1.50
1.525
1.55
1.575
CURRENT
50A/DIV.
HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY
CORE LOAD CURRENT = 31A, 5V LOAD = 5A
SUPPLY FREQUENCY = 200kHz, V IN = 12V
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP
CORE Voltage Programming
The voltage identification pins (VID25mV, VID0, VID1, VID2
and VID3) set the CORE output voltage. Each VID pin is
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1.60
1.625
1.65
1.675
1.70
1.725
1.75
1.775
1.80
1.825
pulled to VCC by an internal 20 μ A current source and
accepts open-collector/open-drain/open-switch-to-ground or
standard low-voltage TTL or CMOS signals.
9
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