参数资料
型号: ISL6553EVAL1
厂商: Intersil
文件页数: 3/9页
文件大小: 0K
描述: EVALUATION BOARD ISL6553
标准包装: 1
系列: Endura™
主要目的: 特殊用途 DC/DC,VRM 电源
输出及类型: 1,非隔离
功率 - 输出: 45W
输出电压: 1.5V
电流 - 输出: 30A
输入电压: 5V,12V
稳压器拓扑结构: 降压
频率 - 开关: 350kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: HIP6601,ISL6553
Application Note AN9961
The leading edge transient response of the ISL6553EVAL1
to the load generator is captured in Figure 4. The core
voltage immediately drops when the transient is applied as
the bulk and ceramic output capacitors begin to support the
output voltage. The controller quickly detects the voltage
deviation and responds by pushing the PWM signals toward
their maximum of 75% for the first pulse following the
transient. The inductor currents rapidly increase to meet this
new demand, supplying an increasing portion of the load.
The inductors assume the majority of load current in about
5 μ s, thereby reducing the bulk capacitance required to
support the transient. The output voltage is quickly driven to
the droop level set for full load of 1.455V.
Output Overcurrent Protection
The ISL6553 monitors the output current level via the ISEN
pins. The R ISEN resistors (R1, R2) are selected such that the
current out of the ISEN pins is 50 μ A at maximum load current.
When excessive load current forces the average of the ISEN
currents to exceed 165% of 50 μ A or 82.5 μ A, the converter
detects an overcurrent event. The ISL6553 immediately
transitions the PWM signals from their current state into a high
impedance state, quickly removing gate drive to the
HIP6601A drivers. The core voltage begins to decay as the
output capacitors discharge. Once the output voltage falls
below the undervoltage threshold, the PGOOD signal
transitions low. This series of events is captured in Figure 6.
1.55V
0A
0V
Core Voltage, 50mv/div
PWM1, 5v/div
PWM2, 5v/div
Inductor Currents, 10A/div
0V
0A
0V
Core Voltage (1V/div)
Output Current (20A/div)
PGOOD (5V/div)
0V
5 μ s/div
0V
PWM1 (5V/div)
FIGURE 4. LEADING EDGE TRANSIENT RESPONSE
Figure 5 shows the core voltage, inductor current and PWM
signals changing in response to the trailing edge of the
transient load current. When the load is removed, the output
voltage rises quickly in response. The controller detects the
0V
PWM2 (5V/div)
50 μ s/div
FIGURE 6. OVERCURRENT RESPONSE
load change and immediately decreases the duty cycle to
zero for one cycle. During this zero duty cycle period, the
output capacitors sustain the output voltage, while the
inductors shed load current at the maximum rate. The output
voltage is brought back to the no-load offset level of 1.545V
in approximately 5 μ s.
1.55V
Core Voltage, 50mV/div
Inductor Currents, 10A/div
0A
After the overcurrent event is detected, the controller waits a
short delay time before attempting a soft-start cycle to allow
the disturbance to clear. The delay time for the
ISL6553EVAL1 board is about 8ms in duration and is set by
the switching frequency of the converter (2048/f SW ). If,
during the soft-start cycle, another overcurrent trip is
detected, the PWM signals are again tri-stated and PGOOD
remains low. The controller waits another 8ms before
another soft-start cycle is attempted.
Figure 7 illustrates how the controller recovers from an
overcurrent trip caused by a temporary short on the output.
After detecting the initial application of the short while
regulating the core under a 30A load, the controller halts
PWM operation and places the PWM outputs into Tri-State ? .
See the PWM1 waveform in Figure 7. A soft-start cycle is
attempted after an 8ms delay. The output remains shorted
0V
0V
PWM1, 10V/div
PWM2, 10V/div
5 μ s/div
FIGURE 5. TRAILING EDGE TRANSIENT RESPONSE
3
during the first soft-start cycle. The ISL6553 detects the
short as an overcurrent event during the soft-start cycle and
places the PWM outputs into Tri-State. The short is removed
during the 8ms delay before initiating a second soft-start
cycle. The converter safely resumes regulation of the 30A
Tri-State? is a registered trademark of National Semiconductor Corp.
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