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| 型号： | ISL6569CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 17/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR DIVIDER PWM 32-QFN |
| 标准包装： | 6,000 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 2MHz |
| 占空比： | 75% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 是 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6569
Balance ). In this case, chose a new, smaller value of R ISEN
for the affected phase. Choose R ISEN,2 in proportion to the
desired decrease in temperature rise in order to cause
proportionally less current to flow in the hotter phase.
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
R ISEN , 2 = R ISEN ---------- 2
? T
? T 1
(EQ. 20)
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
In Equation 20, make sure that ? T 2 is the desired temperature
rise above the ambient temperature, and ? T 1 is the measured
temperature rise above the ambient temperature. While a
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
? V ≈ ( ESL ) ----- + ( ESR ) ? I
single adjustment according to Equation 20 is usually
sufficient, it may occasionally be necessary to adjust R ISEN
two or more times to achieve perfect thermal balance between
di
dt
(EQ. 23)
both channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labeled R FB in Figure 6.
Its value depends on the desired full-load droop voltage
(V DROOP in Figure 6). If Equation 19 is used to select each
ISEN resistor, the load-line regulation resistor is as shown
in Equation 21.
The filter capacitor must have sufficiently low ESL and ESR
so that ? V < ? V MAX .
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance, but limited
high-frequency performance. Minimizing the ESL of the high-
frequency capacitors allows them to support the output
– 6
V DROOP
R FB = -------------------------
50 × 10
(EQ. 21)
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
∑ R ISEN ( n )
V DROOP
R FB = --------------------------------
If one or both of the ISEN resistors was adjusted for thermal
balance, as in Equation 20, the load-line regulation resistor
should be selected according to Equation 22. Where I FL is
the full-load operating current and R ISEN(n) is the ISEN
resistor connected to the n th ISEN pin.
(EQ. 22)
I FL r DS ( ON ) n
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see Interleaving and
Equation 2), a voltage develops across the bulk-capacitor
ESR equal to I C,P P (ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage,
V PP(MAX) , determines the lower limit on the inductance.
? V ?
Output Filter Design
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the pulsating
? IN – 2V OUT ? V OUT
L ≥ ( ESR ) ----------------------------------------------------------
f S V IN V PP ( MAX )
(EQ. 24)
voltage at the phase nodes. The output filter also must
provide the transient energy during the interval of time after
the beginning of the transient until the regulator can respond.
Because it has a low bandwidth compared to the switching
frequency, the output filter necessarily limits the system
transient response leaving the output capacitor bank to
supply or sink load current while the current in the output
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
? V MAX . This places an upper limits on inductance.
L ≤ ---------------- ? V MAX – ? I ( ESR )
L ≤ ----------------- ? V MAX – ? I ( ESR ) ? V IN – V O ?
( ? I ) 2
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ? I; the load-current slew rate, di/dt; and the
4CV O
( ? I ) 2
( 2.5 ) C
? ?
(EQ. 25)
(EQ. 26)
maximum allowable output-voltage deviation under transient
loading, ? V MAX . Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
17
Equation 26 gives the upper limit on L for the cases when the
trailing edge of the current transient causes a greater output-
voltage deviation than the leading edge. Equation 25
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
FN9085.7
December 29, 2004
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