参数资料
| 型号： | ISL6571CRZ |
| 厂商： | Intersil |
| 文件页数： | 9/11页 |
| 文件大小： | 0K |
| 描述： | IC MOSF DRVR/SYNC SW COMPL 68QFN |
| 标准包装： | 168 |
| 类型： | 半桥 |
| 输入类型： | PWM |
| 电流 - 输出 / 通道： | 25A |
| 电源电压： | 10.8 V ~ 13.2 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 68-VFQFN 裸露焊盘 |
| 供应商设备封装： | 68-QFN 裸露焊盘（10x10） |
| 包装： | 管件 |
ISL6571
Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the surrounding application to
TO PWM
TO +12V
C BULK
C BOOT
TO V IN
the ISL6571 should be sized according to their task. Thus,
small-signal traces, like the PWM signal or the ISEN
feedback (if used in conjunction with another Intersil
controller), only need be as wide as 5-10mils. Traces
carrying bias current should be larger, proportionately with
the current flowing through them; for example, traces
TO +5V
C VCC
GND
VIN
carrying PVCC current around 50-100mA would require
30-50mils. Generally, the best connections are the shortest,
C PVCC
PHASE
C HF (x2)
enclosing the least amount of area possible. Similarly, from a
conduction requirement perspective, where vias are required
to carry current, use a via for each 2-3A of RMS current.
Bootstrap Requirements
The ISL6571 features an integrated boot element connected
between the PVCC and BOOT pins. A 0.1 μ F external
bootstrap capacitor is recommended.
TO L OUT
KEY
ISLAND ON POWER PLANE LAYER
CONNECTING TRACES ON TOP/BOTTOM LAYERS
VIA CONNECTION TO OTHER PLANEs
FIGURE 12. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
Use copper-filled polygons on the top and bottom circuit
layers for the PHASE node, but do not unnecessarily
oversize these particular islands. Since the PHASE node is
subject to very high dV/dt voltages, the stray capacitors
formed between these islands and the surrounding circuitry
or internal planes will tend to couple switching noise. On the
other hand, these islands have to be sufficiently large to offer
a good path to surrounding environment for the heat
produced inside the ISL6571.
Capacitor (Decoupling) Selection
To fully extract the benefits of a highly performant power
integrated circuit, the circuit elements surrounding it must
conform to the same high standards as the active power
element. As such, the capacitors used for high-frequency
decoupling of the ISL6571 should be good quality ceramic,
with a low ESR and ESL (X7R, X5R dielectric, and 0805 or
smaller footprints recommended); a minimum of two 1 μ F
capacitors are recommended. Bulk decoupling capacitor
technology is not restricted to ceramic, as electrolytic
capacitors are also suitable. For best results, select
capacitors based on the input RMS current draw of the
circuit, with a low ESL; distribute evenly amongst and place
them as close to the ISL6571 as possible.
ISL6571 DC-DC Converter Application
Circuit
Figure 13 shows an application circuit of a power supply for
a microprocessor computer system. For detailed information
on the circuit, including a Bill-of-Materials and circuit board
description, contact Intersil to order the evaluation kit
ISL6571EVAL1. Also see Intersil web page
(http://www.intersil.com).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN9082.4
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