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| 型号： | ISL6594DCBZ-T |
| 厂商： | Intersil |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR SYNC BUCK 8-SOIC |
| 标准包装： | 2,500 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 10ns |
| 电流 - 峰： | 1.25A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 36V |
| 电源电压： | 6.8 V ~ 13.2 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
ISL6594D
thresholds outlined in the “Electrical Specifications” on
page 4 determine when the lower and upper gates are
enabled.
This feature helps prevent a negative transient on the output
voltage when the output is shut down, eliminating the
Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.
In addition, more than 400mV hysteresis also incorporates
into the three-state shutdown window to eliminate PWM
input oscillations due to the capacitive load seen by the
PWM input through the body diode of the controller ’s PWM
output when the power-up and/or power-down sequence of
bias supplies of the driver and PWM controller are required.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 6.4V (typically),
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the
falling threshold of 5.0V (typically), operation of the driver is
disabled.
where Q G1 is the amount of gate charge per upper MOSFET
at V GS1 gate-source voltage and N Q1 is the number of
control MOSFETs. The DV BOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive.
As an example, suppose two IRLR7821 FETs are chosen as
the upper MOSFETs. The gate charge, Q G , from the data
sheet is 10nC at 4.5V (V GS ) gate-source voltage. Then the
Q GATE is calculated to be 53nC for PVCC = 12V. We will
assume a 200mV droop in drive voltage over the PWM
cycle. We find that a bootstrap capacitance of at least
0.267 μ F is required.
1.6
1.4
1.2
1.0
0.8
0.6
Pre-POR Overvoltage Protection
Prior to VCC exceeding its POR level, the upper gate is held
low and the lower gate is controlled by the overvoltage
0.4
0.2
20nC
Q GATE = 100nC
50nC
protection circuits. The upper gate driver is powered from
PVCC and will be held low when a voltage of 2.75V or higher
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
is present on PVCC as VCC surpasses its POR threshold.
The PHASE is connected to the gate of the low side
MOSFET (LGATE), which provides some protection to the
microprocessor if the upper MOSFET(s) is shorted during
start-up, normal, or shutdown conditions. For complete
protection, the low side MOSFET should have a gate
threshold well below the maximum voltage rating of the
load/microprocessor.
Internal Bootstrap Device
Both drivers feature an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V and its capacitance value can be
chosen from Equation 1:
Δ V BOOT_CAP (V)
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6594D provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The ISL6594D
ties the upper and lower drive rails together. Simply applying
a voltage from +4.5V up to 13.2V on PVCC sets both gate
drive rail voltages simultaneously, while VCC’s operating
range is from +6.8V up to 13.2V. For 5V operation,
ISL6596/ISL6609 is recommended.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (f SW ), the output drive impedance, the
external gate resistance, and the selected MOSFET’s internal
gate resistance and total gate charge. Calculating the power
dissipation in the driver for a desired application is critical to
ensure safe operation. Exceeding the maximum allowable
power dissipation level will push the IC beyond the maximum
C BOOT_CAP ≥ --------------------------------------
Q GATE = ------------------------------------ ? N Q1
Q GATE
Δ V BOOT_CAP
Q G1 ? PVCC
V GS1
7
(EQ. 1)
recommended operating junction temperature of +125°C. The
maximum allowable IC power dissipation for the SO8 package
is approximately 800mW at room temperature, while the
power dissipation capacity in the DFN package, with an
exposed heat escape pad, is more than 1.5W. The DFN
package is more suitable for high frequency applications. See
“ Layout Considerations ” on page 8 for thermal transfer
FN9282.1
December 3, 2007
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