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| 型号： | ISL6594DCBZ-T |
| 厂商： | Intersil |
| 文件页数： | 9/11页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR SYNC BUCK 8-SOIC |
| 标准包装： | 2,500 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 10ns |
| 电流 - 峰： | 1.25A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 36V |
| 电源电压： | 6.8 V ~ 13.2 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
ISL6594D
vias. This combination of vias for vertical heat escape,
extended copper plane, and buried planes for heat
spreading allows the IC to achieve its full thermal potential.
Upper MOSFET Self Turn-On Effects at Start-up
PVCC
BOOT
C BOOT
C GD
VIN
D
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, because of
self-coupling via the internal C GD of the MOSFET, the
DU
DL
UGATE
G
R GI
C GS
C DS
Q UPPER
UGATE could momentarily rise up to a level greater than the
threshold voltage of the MOSFET. This could potentially turn
on the upper switch and result in damaging inrush energy.
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is a common practice to
place a resistor (R UGPH ) across the gate and source of the
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the C GD /C GS ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
C DS /C GS ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, a
5k Ω to 10k Ω resistor is typically sufficient, not affecting
normal performance and efficiency.
The coupling effect can be roughly estimated using
Equation 5, which assume a fixed linear input ramp and
neglect the clamping effect of the body diode of the upper
drive and the bootstrap capacitor. Other parasitic
components such as lead inductances and PCB
capacitances are also not taken into account. These
equations are provided for guidance purpose only.
Therefore, the actual coupling effect should be examined
using a very high impedance (10M Ω or greater) probe to
ensure a safe design margin.
S
PHASE
FIGURE 5. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
– V
?
---------------------------------- ?
? dV ?
V GS_MILLER = ------- ? R ? C rss ? 1 – e dt
iss ?
------ ? R ? C
dV
DS
dt ? ?
? ?
? ?
(EQ. 5)
R = R UGPH + R GI
C rss = C GD
9
C iss = C GD + C GS
FN9282.1
December 3, 2007
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| ISL6595DRZ-T | 功能描述:IC DIGITL MULTIPHASE CTRLR 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
| ISL6595DRZ-TK | 功能描述:IC DIGITL MULTIPHASE CTRLR 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
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