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| 型号： | ISL6612AEIBZ-T |
| 厂商： | Intersil |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR SYNC BUCK 8EPSOIC |
| 标准包装： | 2,500 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 10ns |
| 电流 - 峰： | 1.25A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 36V |
| 电源电压： | 10.8 V ~ 13.2 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 供应商设备封装： | 8-SOIC-EP |
| 包装： | 带卷 (TR) |
ISL6612A, ISL6613A
thermal transfer improvement suggestions. When designing
the driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
desired frequency for thresholds outlined in the
UVCC
BOOT
C GD
D
ELECTRICAL SPECIFICATIONS determine when the lower
and upper gates are enabled.
the selected MOSFETs. The total gate drive power losses
due to the gate charge of MOSFETs and the driver ’s internal
circuitry and their corresponding average driver current can
R HI1
R LO1
G
R G1
R GI1
C GS
S
C DS
Q1
be estimated with Equations 2 and 3, respectively,
PHASE
P Qg_Q1 = --------------------------------------- ? F SW ? N Q1
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
Q G1 ? UVCC 2
V GS1
(EQ. 2)
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
LVCC
P Qg_Q2 = -------------------------------------- ? F SW ? N Q2
Q G2 ? LVCC 2
V GS2
R HI2
G
C GD
D
C DS
I DR = ? ------------------------------------------------------ + ----------------------------------------------------- ? ? F SW + I Q
? Q G1 ? UVCC ? N Q1 Q G2 ? LVCC ? N Q2 ?
? V GS1 V GS2 ?
R LO2
R G2
R GI2
C GS
Q2
(EQ. 3)
where the gate charge (Q G1 and Q G2 ) is defined at a
particular gate to source voltage (V GS1 and V GS2 ) in the
corresponding MOSFET datasheet; I Q is the driver ’s total
quiescent current with no load at both drive outputs; N Q1
and N Q2 are number of upper and lower MOSFETs,
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I Q* VCC
product is the quiescent power of the driver without
capacitive load and is typically 116mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R G1 and R G2 ) and the internal gate resistors
(R GI1 and R GI2 ) of MOSFETs. Figures 3 and 4 show the
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:
S
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
P DR_LOW = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI2 + R EXT2 R LO2 + R EXT2 ?
R EXT1 = R G1 + -------------
N
R EXT2 = R G2 + -------------
N
P DR = P DR_UP + P DR_LOW + I Q ? VCC
? R HI1 R LO1 ? P Qg_Q1
? R HI2 R LO2 ? P Qg_Q2
R GI1
Q1
9
2
2
R GI2
Q2
(EQ. 4)
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
FN9159.7
May 1, 2012
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6612AIB | 制造商:Intersil Corporation 功能描述: |
| ISL6612AIBZ | 功能描述:IC MOSFET DRVR SYNC BUCK 8-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:50 系列:- 配置:高端 输入类型:非反相 延迟时间:200ns 电流 - 峰:250mA 配置数:1 输出数:1 高端电压 - 最大（自引导启动）:600V 电源电压:12 V ~ 20 V 工作温度:-40°C ~ 125°C 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-DIP 包装:管件 其它名称:*IR2127 |
| ISL6612AIBZ-T | 功能描述:IC MOSFET DRVR SYNC BUCK 8-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:6,000 系列:* |
| ISL6612AIR | 功能描述:IC MOSFET DRVR SYNC BUCK 10-DFN RoHS:否 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:50 系列:- 配置:低端 输入类型:非反相 延迟时间:40ns 电流 - 峰:9A 配置数:1 输出数:1 高端电压 - 最大（自引导启动）:- 电源电压:4.5 V ~ 35 V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-6，D²Pak（5 引线+接片），TO-263BA 供应商设备封装:TO-263 包装:管件 |
| ISL6612AIR-T | 功能描述:IC MOSFET DRVR SYNC BUCK 10-DFN RoHS:否 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:50 系列:- 配置:低端 输入类型:非反相 延迟时间:40ns 电流 - 峰:9A 配置数:1 输出数:1 高端电压 - 最大（自引导启动）:- 电源电压:4.5 V ~ 35 V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-6，D²Pak（5 引线+接片），TO-263BA 供应商设备封装:TO-263 包装:管件 |
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